Commit cbe1f838 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain 



Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 3f3f0ea0

arch/arm/boot/dts/r7s72100.dtsi

+19 −0
Original line number Original line Diff line number Diff line
@@ -86,6 +86,7 @@ cpg_clocks: cpg_clocks@fcfe0000 { 
			reg = <0xfcfe0000 0x18>;

			reg = <0xfcfe0000 0x18>;

			clocks = <&extal_clk>, <&usb_x1_clk>;

			clocks = <&extal_clk>, <&usb_x1_clk>;

			clock-output-names = "pll", "i", "g";

			clock-output-names = "pll", "i", "g";

			#power-domain-cells = <0>;

		};

		};





		/* MSTP clocks */

		/* MSTP clocks */
@@ -157,6 +158,7 @@ scif0: serial@e8007000 { 
			     <0 189 IRQ_TYPE_LEVEL_HIGH>;

			     <0 189 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;

		clock-names = "sci_ick";

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -169,6 +171,7 @@ scif1: serial@e8007800 { 
			     <0 193 IRQ_TYPE_LEVEL_HIGH>;

			     <0 193 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;

		clock-names = "sci_ick";

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -181,6 +184,7 @@ scif2: serial@e8008000 { 
			     <0 197 IRQ_TYPE_LEVEL_HIGH>;

			     <0 197 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;

		clock-names = "sci_ick";

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -193,6 +197,7 @@ scif3: serial@e8008800 { 
			     <0 201 IRQ_TYPE_LEVEL_HIGH>;

			     <0 201 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;

		clock-names = "sci_ick";

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -205,6 +210,7 @@ scif4: serial@e8009000 { 
			     <0 205 IRQ_TYPE_LEVEL_HIGH>;

			     <0 205 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;

		clock-names = "sci_ick";

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -217,6 +223,7 @@ scif5: serial@e8009800 { 
			     <0 209 IRQ_TYPE_LEVEL_HIGH>;

			     <0 209 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;

		clock-names = "sci_ick";

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -229,6 +236,7 @@ scif6: serial@e800a000 { 
			     <0 213 IRQ_TYPE_LEVEL_HIGH>;

			     <0 213 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;

		clock-names = "sci_ick";

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -241,6 +249,7 @@ scif7: serial@e800a800 { 
			     <0 217 IRQ_TYPE_LEVEL_HIGH>;

			     <0 217 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;

		clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;

		clock-names = "sci_ick";

		clock-names = "sci_ick";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -252,6 +261,7 @@ spi0: spi@e800c800 { 
			     <0 240 IRQ_TYPE_LEVEL_HIGH>;

			     <0 240 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI0>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		num-cs = <1>;

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		#size-cells = <0>;
@@ -266,6 +276,7 @@ spi1: spi@e800d000 { 
			     <0 243 IRQ_TYPE_LEVEL_HIGH>;

			     <0 243 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI1>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		num-cs = <1>;

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		#size-cells = <0>;
@@ -280,6 +291,7 @@ spi2: spi@e800d800 { 
			     <0 246 IRQ_TYPE_LEVEL_HIGH>;

			     <0 246 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI2>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		num-cs = <1>;

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		#size-cells = <0>;
@@ -294,6 +306,7 @@ spi3: spi@e800e000 { 
			     <0 249 IRQ_TYPE_LEVEL_HIGH>;

			     <0 249 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI3>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		num-cs = <1>;

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		#size-cells = <0>;
@@ -308,6 +321,7 @@ spi4: spi@e800e800 { 
			     <0 252 IRQ_TYPE_LEVEL_HIGH>;

			     <0 252 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "error", "rx", "tx";

		interrupt-names = "error", "rx", "tx";

		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;

		clocks = <&mstp10_clks R7S72100_CLK_SPI4>;

		power-domains = <&cpg_clocks>;

		num-cs = <1>;

		num-cs = <1>;

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		#size-cells = <0>;
@@ -338,6 +352,7 @@ i2c0: i2c@fcfee000 { 
			     <0 164 IRQ_TYPE_LEVEL_HIGH>;

			     <0 164 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C0>;

		clock-frequency = <100000>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -356,6 +371,7 @@ i2c1: i2c@fcfee400 { 
			     <0 172 IRQ_TYPE_LEVEL_HIGH>;

			     <0 172 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C1>;

		clock-frequency = <100000>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -374,6 +390,7 @@ i2c2: i2c@fcfee800 { 
			     <0 180 IRQ_TYPE_LEVEL_HIGH>;

			     <0 180 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C2>;

		clock-frequency = <100000>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -392,6 +409,7 @@ i2c3: i2c@fcfeec00 { 
			     <0 188 IRQ_TYPE_LEVEL_HIGH>;

			     <0 188 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;

		clocks = <&mstp9_clks R7S72100_CLK_I2C3>;

		clock-frequency = <100000>;

		clock-frequency = <100000>;

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};
@@ -402,6 +420,7 @@ mtu2: timer@fcff0000 { 
		interrupt-names = "tgi0a";

		interrupt-names = "tgi0a";

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clocks = <&mstp3_clks R7S72100_CLK_MTU2>;

		clock-names = "fck";

		clock-names = "fck";

		power-domains = <&cpg_clocks>;

		status = "disabled";

		status = "disabled";

	};

	};

};
 
};