Commit cdbf0eb4 authored by Ben Hutchings's avatar Ben Hutchings Committed by David S. Miller
Browse files

ixgb: Use generic MDIO definitions 



Compile-tested only.

Signed-off-by: default avatarBen Hutchings <bhutchings@solarflare.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6b73e10d

drivers/net/ixgb/ixgb_hw.c

+10 −10
Original line number Original line Diff line number Diff line
@@ -192,7 +192,7 @@ ixgb_identify_xpak_vendor(struct ixgb_hw *hw) 
		vendor_name[i] = ixgb_read_phy_reg(hw,

		vendor_name[i] = ixgb_read_phy_reg(hw,

						   MDIO_PMA_PMD_XPAK_VENDOR_NAME

						   MDIO_PMA_PMD_XPAK_VENDOR_NAME

						   + i, IXGB_PHY_ADDRESS,

						   + i, IXGB_PHY_ADDRESS,

						   MDIO_PMA_PMD_DID);

						   MDIO_MMD_PMAPMD);

	}

	}





	/* Determine the actual vendor */

	/* Determine the actual vendor */
@@ -1225,15 +1225,15 @@ ixgb_optics_reset(struct ixgb_hw *hw) 
		u16 mdio_reg;

		u16 mdio_reg;





		ixgb_write_phy_reg(hw,

		ixgb_write_phy_reg(hw,

					MDIO_PMA_PMD_CR1,

				   MDIO_CTRL1,

				   IXGB_PHY_ADDRESS,

				   IXGB_PHY_ADDRESS,

					MDIO_PMA_PMD_DID,

				   MDIO_MMD_PMAPMD,

					MDIO_PMA_PMD_CR1_RESET);

				   MDIO_CTRL1_RESET);





		mdio_reg = ixgb_read_phy_reg(hw,

		mdio_reg = ixgb_read_phy_reg(hw,

						MDIO_PMA_PMD_CR1,

					     MDIO_CTRL1,

					     IXGB_PHY_ADDRESS,

					     IXGB_PHY_ADDRESS,

						MDIO_PMA_PMD_DID);

					     MDIO_MMD_PMAPMD);

	}

	}





	return;

	return;

drivers/net/ixgb/ixgb_hw.h

+2 −12
Original line number Original line Diff line number Diff line
@@ -29,6 +29,8 @@ 
#ifndef _IXGB_HW_H_

#ifndef _IXGB_HW_H_

#define _IXGB_HW_H_

#define _IXGB_HW_H_





#include <linux/mdio.h>



#include "ixgb_osdep.h"

#include "ixgb_osdep.h"





/* Enums */

/* Enums */
@@ -507,18 +509,6 @@ typedef enum { 
/* Definitions for the optics devices on the MDIO bus. */

/* Definitions for the optics devices on the MDIO bus. */

#define IXGB_PHY_ADDRESS             0x0	/* Single PHY, multiple "Devices" */

#define IXGB_PHY_ADDRESS             0x0	/* Single PHY, multiple "Devices" */





/* Standard five-bit Device IDs.  See IEEE 802.3ae, clause 45 */

#define MDIO_PMA_PMD_DID        0x01

#define MDIO_WIS_DID            0x02

#define MDIO_PCS_DID            0x03

#define MDIO_XGXS_DID           0x04



/* Standard PMA/PMD registers and bit definitions. */

/* Note: This is a very limited set of definitions,      */

/* only implemented features are defined.                */

#define MDIO_PMA_PMD_CR1        0x0000

#define MDIO_PMA_PMD_CR1_RESET  0x8000



#define MDIO_PMA_PMD_XPAK_VENDOR_NAME       0x803A	/* XPAK/XENPAK devices only */

#define MDIO_PMA_PMD_XPAK_VENDOR_NAME       0x803A	/* XPAK/XENPAK devices only */





/* Vendor-specific MDIO registers */

/* Vendor-specific MDIO registers */