Commit ce075e75 authored by Leo Li's avatar Leo Li Committed by Alex Deucher
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drm/amd/display: Fix DC definition of PMFW Pstate table for DCN316 



[Why]

During DC init, we read power management tables from PMFW. This info is
exchanged in the form of a binary blob inside gpu memory. In order to
parse the binary blob, the correct struct needs to be used.

[How]

Fix dcn316's definition of the DfPstateTable_t struct to align with PMFW

Signed-off-by: default avatarLeo Li <sunpeng.li@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2656fd23

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c

+10 −1
Original line number Diff line number Diff line
@@ -530,7 +530,16 @@ static void dcn316_clk_mgr_helper_populate_bw_params( 
		bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;

		bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;

		bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;

		switch (clock_table->DfPstateTable[j].WckRatio) {

		case WCK_RATIO_1_2:

			bw_params->clk_table.entries[i].wck_ratio = 2;

			break;

		case WCK_RATIO_1_4:

			bw_params->clk_table.entries[i].wck_ratio = 4;

			break;

		default:

			bw_params->clk_table.entries[i].wck_ratio = 1;

		}

		temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);

		if (temp)

			bw_params->clk_table.entries[i].dcfclk_mhz = temp;

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h

+9 −0
Original line number Diff line number Diff line
@@ -57,10 +57,19 @@ typedef enum { 
  WM_COUNT,

} WM_CLOCK_e;



typedef enum{

  WCK_RATIO_1_1 = 0,  // DDR5, Wck:ck is always 1:1;

  WCK_RATIO_1_2,

  WCK_RATIO_1_4,

  WCK_RATIO_MAX

} WCK_RATIO_e;



typedef struct {

  uint32_t FClk;

  uint32_t MemClk;

  uint32_t Voltage;

  uint8_t  WckRatio;

  uint8_t  Spare[3];

} DfPstateTable_t;



//Freq in MHz