Commit ce459b1d authored Nov 07, 2022 by Pierre Gondois Committed by Matthias Brugger Nov 08, 2022

arm64: dts: Update cache properties for mediatek



The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Link: https://lore.kernel.org/r/20221107155825.1644604-13-pierre.gondois@arm.com


Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

parent 9abf2313

arch/arm64/boot/dts/mediatek/mt8186.dtsi

+3 −0

Original line number	Diff line number	Diff line
		@@ -198,16 +198,19 @@ cluster_off_b: cluster-off-b {

		l2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		next-level-cache = <&l3_0>;
		};

		l2_1: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		next-level-cache = <&l3_0>;
		};

		l3_0: l3-cache {
		compatible = "cache";
		cache-level = <3>;
		};
		};

arch/arm64/boot/dts/mediatek/mt8192.dtsi

+3 −0

Original line number	Diff line number	Diff line
		@@ -169,16 +169,19 @@ core3 {

		l2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		next-level-cache = <&l3_0>;
		};

		l2_1: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		next-level-cache = <&l3_0>;
		};

		l3_0: l3-cache {
		compatible = "cache";
		cache-level = <3>;
		};

		idle-states {

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+3 −0

Original line number	Diff line number	Diff line
		@@ -213,16 +213,19 @@ cluster_off_b: cluster-off-b {

		l2_0: l2-cache0 {
		compatible = "cache";
		cache-level = <2>;
		next-level-cache = <&l3_0>;
		};

		l2_1: l2-cache1 {
		compatible = "cache";
		cache-level = <2>;
		next-level-cache = <&l3_0>;
		};

		l3_0: l3-cache {
		compatible = "cache";
		cache-level = <3>;
		};
		};