Commit ce76de98 authored by Heiko Stuebner's avatar Heiko Stuebner
Browse files

ARM: dts: rockchip: convert rk3288 to operating-points-v2 



Operating points need to be present in each cpu core using it, not only
the first one. With operating-points-v1 this would require duplicating
this table into each cpu node.

With opp-v2 we can share the same table on all nodes.

Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent 0bac06df

arch/arm/boot/dts/rk3288-veyron.dtsi

+20 −16
Original line number Original line Diff line number Diff line
@@ -91,22 +91,26 @@ vcc50_hdmi: vcc50-hdmi { 




&cpu0 {

&cpu0 {

	cpu0-supply = <&vdd_cpu>;

	cpu0-supply = <&vdd_cpu>;

	operating-points = <

};

		/* KHz    uV */



		1800000 1400000

/* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */

		1704000 1350000

&cpu_opp_table {

		1608000 1300000

	/delete-node/ opp-312000000;

		1512000 1250000



		1416000 1200000

	opp-1512000000 {

		1200000 1100000

		opp-microvolt = <1250000>;

		1008000 1050000

	};

		 816000 1000000

	opp-1608000000 {

		 696000  950000

		opp-microvolt = <1300000>;

		 600000  900000

	};

		 408000  900000

	opp-1704000000 {

		 216000  900000

		opp-hz = /bits/ 64 <1704000000>;

		 126000  900000

		opp-microvolt = <1350000>;

	>;

	};

	opp-1800000000 {

		opp-hz = /bits/ 64 <1800000000>;

		opp-microvolt = <1400000>;

	};

};

};





&emmc {

&emmc {

arch/arm/boot/dts/rk3288.dtsi

+55 −15
Original line number Original line Diff line number Diff line
@@ -60,21 +60,7 @@ cpu0: cpu@500 { 
			compatible = "arm,cortex-a12";

			compatible = "arm,cortex-a12";

			reg = <0x500>;

			reg = <0x500>;

			resets = <&cru SRST_CORE0>;

			resets = <&cru SRST_CORE0>;

			operating-points = <

			operating-points-v2 = <&cpu_opp_table>;

				/* KHz    uV */

				1608000 1350000

				1512000 1300000

				1416000 1200000

				1200000 1100000

				1008000 1050000

				 816000 1000000

				 696000  950000

				 600000  900000

				 408000  900000

				 312000  900000

				 216000  900000

				 126000  900000

			>;

			#cooling-cells = <2>; /* min followed by max */

			#cooling-cells = <2>; /* min followed by max */

			clock-latency = <40000>;

			clock-latency = <40000>;

			clocks = <&cru ARMCLK>;

			clocks = <&cru ARMCLK>;
@@ -99,6 +85,60 @@ cpu3: cpu@503 { 
		};

		};

	};

	};





	cpu_opp_table: cpu-opp-table {

		compatible = "operating-points-v2";

		opp-shared;



		opp-126000000 {

			opp-hz = /bits/ 64 <126000000>;

			opp-microvolt = <900000>;

		};

		opp-216000000 {

			opp-hz = /bits/ 64 <216000000>;

			opp-microvolt = <900000>;

		};

		opp-312000000 {

			opp-hz = /bits/ 64 <312000000>;

			opp-microvolt = <900000>;

		};

		opp-408000000 {

			opp-hz = /bits/ 64 <408000000>;

			opp-microvolt = <900000>;

		};

		opp-600000000 {

			opp-hz = /bits/ 64 <600000000>;

			opp-microvolt = <900000>;

		};

		opp-696000000 {

			opp-hz = /bits/ 64 <696000000>;

			opp-microvolt = <950000>;

		};

		opp-816000000 {

			opp-hz = /bits/ 64 <816000000>;

			opp-microvolt = <1000000>;

		};

		opp-1008000000 {

			opp-hz = /bits/ 64 <1008000000>;

			opp-microvolt = <1050000>;

		};

		opp-1200000000 {

			opp-hz = /bits/ 64 <1200000000>;

			opp-microvolt = <1100000>;

		};

		opp-1416000000 {

			opp-hz = /bits/ 64 <1416000000>;

			opp-microvolt = <1200000>;

		};

		opp-1512000000 {

			opp-hz = /bits/ 64 <1512000000>;

			opp-microvolt = <1300000>;

		};

		opp-1608000000 {

			opp-hz = /bits/ 64 <1608000000>;

			opp-microvolt = <1350000>;

		};

	};



	amba {

	amba {

		compatible = "simple-bus";

		compatible = "simple-bus";

		#address-cells = <2>;

		#address-cells = <2>;