Commit ce81151c authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amd/smu: add smu v13_0 header files 



Add driver_if ppsmc and pptable header files
for smu v13_0_0

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6a2d7a22

drivers/gpu/drm/amd/pm/inc/smu_v13_0_0_pptable.h

0 → 100644
+200 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 */

#ifndef SMU_13_0_0_PPTABLE_H

#define SMU_13_0_0_PPTABLE_H



#define SMU_13_0_0_TABLE_FORMAT_REVISION 15



//// POWERPLAYTABLE::ulPlatformCaps

#define SMU_13_0_0_PP_PLATFORM_CAP_POWERPLAY 0x1        // This cap indicates whether CCC need to show Powerplay page.

#define SMU_13_0_0_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 0x2 // This cap indicates whether power source notificaiton is done by SBIOS instead of OS.

#define SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC 0x4       // This cap indicates whether DC mode notificaiton is done by GPIO pin directly.

#define SMU_13_0_0_PP_PLATFORM_CAP_BACO 0x8             // This cap indicates whether board supports the BACO circuitry.

#define SMU_13_0_0_PP_PLATFORM_CAP_MACO 0x10            // This cap indicates whether board supports the MACO circuitry.

#define SMU_13_0_0_PP_PLATFORM_CAP_SHADOWPSTATE 0x20    // This cap indicates whether board supports the Shadow Pstate.



// SMU_13_0_0_PP_THERMALCONTROLLER - Thermal Controller Type

#define SMU_13_0_0_PP_THERMALCONTROLLER_NONE 0

#define SMU_13_0_0_PP_THERMALCONTROLLER_NAVI21 28



#define SMU_13_0_0_PP_OVERDRIVE_VERSION 0x81        // OverDrive 8 Table Version 0.2

#define SMU_13_0_0_PP_POWERSAVINGCLOCK_VERSION 0x01 // Power Saving Clock Table Version 1.00



enum SMU_13_0_0_ODFEATURE_CAP

{

    SMU_13_0_0_ODCAP_GFXCLK_LIMITS = 0,

    SMU_13_0_0_ODCAP_GFXCLK_CURVE,

    SMU_13_0_0_ODCAP_UCLK_LIMITS,

    SMU_13_0_0_ODCAP_POWER_LIMIT,

    SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT,

    SMU_13_0_0_ODCAP_FAN_SPEED_MIN,

    SMU_13_0_0_ODCAP_TEMPERATURE_FAN,

    SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM,

    SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE,

    SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL,

    SMU_13_0_0_ODCAP_AUTO_UV_ENGINE,

    SMU_13_0_0_ODCAP_AUTO_OC_ENGINE,

    SMU_13_0_0_ODCAP_AUTO_OC_MEMORY,

    SMU_13_0_0_ODCAP_FAN_CURVE,

    SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT,

    SMU_13_0_0_ODCAP_POWER_MODE,

    SMU_13_0_0_ODCAP_COUNT,

};



enum SMU_13_0_0_ODFEATURE_ID

{

    SMU_13_0_0_ODFEATURE_GFXCLK_LIMITS           = 1 << SMU_13_0_0_ODCAP_GFXCLK_LIMITS,           //GFXCLK Limit feature

    SMU_13_0_0_ODFEATURE_GFXCLK_CURVE            = 1 << SMU_13_0_0_ODCAP_GFXCLK_CURVE,            //GFXCLK Curve feature

    SMU_13_0_0_ODFEATURE_UCLK_LIMITS             = 1 << SMU_13_0_0_ODCAP_UCLK_LIMITS,             //UCLK Limit feature

    SMU_13_0_0_ODFEATURE_POWER_LIMIT             = 1 << SMU_13_0_0_ODCAP_POWER_LIMIT,             //Power Limit feature

    SMU_13_0_0_ODFEATURE_FAN_ACOUSTIC_LIMIT      = 1 << SMU_13_0_0_ODCAP_FAN_ACOUSTIC_LIMIT,      //Fan Acoustic RPM feature

    SMU_13_0_0_ODFEATURE_FAN_SPEED_MIN           = 1 << SMU_13_0_0_ODCAP_FAN_SPEED_MIN,           //Minimum Fan Speed feature

    SMU_13_0_0_ODFEATURE_TEMPERATURE_FAN         = 1 << SMU_13_0_0_ODCAP_TEMPERATURE_FAN,         //Fan Target Temperature Limit feature

    SMU_13_0_0_ODFEATURE_TEMPERATURE_SYSTEM      = 1 << SMU_13_0_0_ODCAP_TEMPERATURE_SYSTEM,      //Operating Temperature Limit feature

    SMU_13_0_0_ODFEATURE_MEMORY_TIMING_TUNE      = 1 << SMU_13_0_0_ODCAP_MEMORY_TIMING_TUNE,      //AC Timing Tuning feature

    SMU_13_0_0_ODFEATURE_FAN_ZERO_RPM_CONTROL    = 1 << SMU_13_0_0_ODCAP_FAN_ZERO_RPM_CONTROL,    //Zero RPM feature

    SMU_13_0_0_ODFEATURE_AUTO_UV_ENGINE          = 1 << SMU_13_0_0_ODCAP_AUTO_UV_ENGINE,          //Auto Under Volt GFXCLK feature

    SMU_13_0_0_ODFEATURE_AUTO_OC_ENGINE          = 1 << SMU_13_0_0_ODCAP_AUTO_OC_ENGINE,          //Auto Over Clock GFXCLK feature

    SMU_13_0_0_ODFEATURE_AUTO_OC_MEMORY          = 1 << SMU_13_0_0_ODCAP_AUTO_OC_MEMORY,          //Auto Over Clock MCLK feature

    SMU_13_0_0_ODFEATURE_FAN_CURVE               = 1 << SMU_13_0_0_ODCAP_FAN_CURVE,               //Fan Curve feature

    SMU_13_0_0_ODFEATURE_AUTO_FAN_ACOUSTIC_LIMIT = 1 << SMU_13_0_0_ODCAP_AUTO_FAN_ACOUSTIC_LIMIT, //Auto Fan Acoustic RPM feature

    SMU_13_0_0_ODFEATURE_POWER_MODE              = 1 << SMU_13_0_0_ODCAP_POWER_MODE,              //Optimized GPU Power Mode feature

    SMU_13_0_0_ODFEATURE_COUNT                   = 16,

};



#define SMU_13_0_0_MAX_ODFEATURE 32 //Maximum Number of OD Features



enum SMU_13_0_0_ODSETTING_ID

{

    SMU_13_0_0_ODSETTING_GFXCLKFMAX = 0,

    SMU_13_0_0_ODSETTING_GFXCLKFMIN,

    SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_A,

    SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_B,

    SMU_13_0_0_ODSETTING_CUSTOM_GFX_VF_CURVE_C,

    SMU_13_0_0_ODSETTING_CUSTOM_CURVE_VFT_FMIN,

    SMU_13_0_0_ODSETTING_UCLKFMIN,

    SMU_13_0_0_ODSETTING_UCLKFMAX,

    SMU_13_0_0_ODSETTING_POWERPERCENTAGE,

    SMU_13_0_0_ODSETTING_FANRPMMIN,

    SMU_13_0_0_ODSETTING_FANRPMACOUSTICLIMIT,

    SMU_13_0_0_ODSETTING_FANTARGETTEMPERATURE,

    SMU_13_0_0_ODSETTING_OPERATINGTEMPMAX,

    SMU_13_0_0_ODSETTING_ACTIMING,

    SMU_13_0_0_ODSETTING_FAN_ZERO_RPM_CONTROL,

    SMU_13_0_0_ODSETTING_AUTOUVENGINE,

    SMU_13_0_0_ODSETTING_AUTOOCENGINE,

    SMU_13_0_0_ODSETTING_AUTOOCMEMORY,

    SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_1,

    SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_1,

    SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_2,

    SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_2,

    SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_3,

    SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_3,

    SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_4,

    SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_4,

    SMU_13_0_0_ODSETTING_FAN_CURVE_TEMPERATURE_5,

    SMU_13_0_0_ODSETTING_FAN_CURVE_SPEED_5,

    SMU_13_0_0_ODSETTING_AUTO_FAN_ACOUSTIC_LIMIT,

    SMU_13_0_0_ODSETTING_POWER_MODE,

    SMU_13_0_0_ODSETTING_COUNT,

};

#define SMU_13_0_0_MAX_ODSETTING 64 //Maximum Number of ODSettings



enum SMU_13_0_0_PWRMODE_SETTING

{

    SMU_13_0_0_PMSETTING_POWER_LIMIT_QUIET = 0,

    SMU_13_0_0_PMSETTING_POWER_LIMIT_BALANCE,

    SMU_13_0_0_PMSETTING_POWER_LIMIT_TURBO,

    SMU_13_0_0_PMSETTING_POWER_LIMIT_RAGE,

    SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_QUIET,

    SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_BALANCE,

    SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_TURBO,

    SMU_13_0_0_PMSETTING_ACOUSTIC_TEMP_RAGE,

    SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_QUIET,

    SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_BALANCE,

    SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_TURBO,

    SMU_13_0_0_PMSETTING_ACOUSTIC_TARGET_RPM_RAGE,

    SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_QUIET,

    SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_BALANCE,

    SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_TURBO,

    SMU_13_0_0_PMSETTING_ACOUSTIC_LIMIT_RPM_RAGE,

};

#define SMU_13_0_0_MAX_PMSETTING 32 //Maximum Number of PowerMode Settings



struct smu_13_0_0_overdrive_table

{

    uint8_t revision;                             //Revision = SMU_13_0_0_PP_OVERDRIVE_VERSION

    uint8_t reserve[3];                           //Zero filled field reserved for future use

    uint32_t feature_count;                       //Total number of supported features

    uint32_t setting_count;                       //Total number of supported settings

    uint8_t cap[SMU_13_0_0_MAX_ODFEATURE];        //OD feature support flags

    uint32_t max[SMU_13_0_0_MAX_ODSETTING];       //default maximum settings

    uint32_t min[SMU_13_0_0_MAX_ODSETTING];       //default minimum settings

    int16_t pm_setting[SMU_13_0_0_MAX_PMSETTING]; //Optimized power mode feature settings

};



enum SMU_13_0_0_PPCLOCK_ID

{

    SMU_13_0_0_PPCLOCK_GFXCLK = 0,

    SMU_13_0_0_PPCLOCK_SOCCLK,

    SMU_13_0_0_PPCLOCK_UCLK,

    SMU_13_0_0_PPCLOCK_FCLK,

    SMU_13_0_0_PPCLOCK_DCLK_0,

    SMU_13_0_0_PPCLOCK_VCLK_0,

    SMU_13_0_0_PPCLOCK_DCLK_1,

    SMU_13_0_0_PPCLOCK_VCLK_1,

    SMU_13_0_0_PPCLOCK_DCEFCLK,

    SMU_13_0_0_PPCLOCK_DISPCLK,

    SMU_13_0_0_PPCLOCK_PIXCLK,

    SMU_13_0_0_PPCLOCK_PHYCLK,

    SMU_13_0_0_PPCLOCK_DTBCLK,

    SMU_13_0_0_PPCLOCK_COUNT,

};

#define SMU_13_0_0_MAX_PPCLOCK 16 //Maximum Number of PP Clocks



struct smu_13_0_0_powerplay_table

{

    struct atom_common_table_header header; //For SMU13, header.format_revision = 15, header.content_revision = 0

    uint8_t table_revision;                 //For SMU13, table_revision = 2

    uint8_t padding;

    uint16_t table_size;                    //Driver portion table size. The offset to smc_pptable including header size

    uint32_t golden_pp_id;                  //PPGen use only: PP Table ID on the Golden Data Base

    uint32_t golden_revision;               //PPGen use only: PP Table Revision on the Golden Data Base

    uint16_t format_id;                     //PPGen use only: PPTable for different ASICs. For SMU13 this should be 0x80

    uint32_t platform_caps;                 //POWERPLAYABLE::ulPlatformCaps



    uint8_t thermal_controller_type; //one of SMU_13_0_0_PP_THERMALCONTROLLER



    uint16_t small_power_limit1;

    uint16_t small_power_limit2;

    uint16_t boost_power_limit; //For Gemini Board, when the slave adapter is in BACO mode, the master adapter will use this boost power limit instead of the default power limit to boost the power limit.

    uint16_t software_shutdown_temp;



    uint32_t reserve[45];



    struct smu_13_0_0_overdrive_table overdrive_table;

    uint8_t padding1;

    PPTable_t smc_pptable; //PPTable_t in driver_if.h

} __attribute__((packed));





#endif

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_0.h

0 → 100644
+1544 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_0_ppsmc.h

0 → 100644
+141 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef SMU_V13_0_0_PPSMC_H

#define SMU_V13_0_0_PPSMC_H



#define PPSMC_VERSION 0x1

#define DEBUGSMC_VERSION    0x1



// SMU Response Codes:

#define PPSMC_Result_OK                    0x1

#define PPSMC_Result_Failed                0xFF

#define PPSMC_Result_UnknownCmd            0xFE

#define PPSMC_Result_CmdRejectedPrereq     0xFD

#define PPSMC_Result_CmdRejectedBusy       0xFC



// Message Definitions:

// BASIC

#define PPSMC_MSG_TestMessage                    0x1

#define PPSMC_MSG_GetSmuVersion                  0x2

#define PPSMC_MSG_GetDriverIfVersion             0x3

#define PPSMC_MSG_SetAllowedFeaturesMaskLow      0x4

#define PPSMC_MSG_SetAllowedFeaturesMaskHigh     0x5

#define PPSMC_MSG_EnableAllSmuFeatures           0x6

#define PPSMC_MSG_DisableAllSmuFeatures          0x7

#define PPSMC_MSG_EnableSmuFeaturesLow           0x8

#define PPSMC_MSG_EnableSmuFeaturesHigh          0x9

#define PPSMC_MSG_DisableSmuFeaturesLow          0xA

#define PPSMC_MSG_DisableSmuFeaturesHigh         0xB

#define PPSMC_MSG_GetRunningSmuFeaturesLow       0xC

#define PPSMC_MSG_GetRunningSmuFeaturesHigh      0xD

#define PPSMC_MSG_SetDriverDramAddrHigh          0xE

#define PPSMC_MSG_SetDriverDramAddrLow           0xF

#define PPSMC_MSG_SetToolsDramAddrHigh           0x10

#define PPSMC_MSG_SetToolsDramAddrLow            0x11

#define PPSMC_MSG_TransferTableSmu2Dram          0x12

#define PPSMC_MSG_TransferTableDram2Smu          0x13

#define PPSMC_MSG_UseDefaultPPTable              0x14



//BACO/BAMACO/BOMACO

#define PPSMC_MSG_EnterBaco                      0x15

#define PPSMC_MSG_ExitBaco                       0x16

#define PPSMC_MSG_ArmD3                          0x17

#define PPSMC_MSG_BacoAudioD3PME                 0x18



//DPM

#define PPSMC_MSG_SetSoftMinByFreq               0x19

#define PPSMC_MSG_SetSoftMaxByFreq               0x1A

#define PPSMC_MSG_SetHardMinByFreq               0x1B

#define PPSMC_MSG_SetHardMaxByFreq               0x1C

#define PPSMC_MSG_GetMinDpmFreq                  0x1D

#define PPSMC_MSG_GetMaxDpmFreq                  0x1E

#define PPSMC_MSG_GetDpmFreqByIndex              0x1F

#define PPSMC_MSG_OverridePcieParameters         0x20



//DramLog Set DramAddr

#define PPSMC_MSG_DramLogSetDramAddrHigh         0x21

#define PPSMC_MSG_DramLogSetDramAddrLow          0x22

#define PPSMC_MSG_DramLogSetDramSize             0x23

#define PPSMC_MSG_SetWorkloadMask                0x24



#define PPSMC_MSG_GetVoltageByDpm                0x25

#define PPSMC_MSG_SetVideoFps                    0x26

#define PPSMC_MSG_GetDcModeMaxDpmFreq            0x27



//Power Gating

#define PPSMC_MSG_AllowGfxOff                    0x28

#define PPSMC_MSG_DisallowGfxOff                 0x29

#define PPSMC_MSG_PowerUpVcn                     0x2A

#define PPSMC_MSG_PowerDownVcn	                 0x2B

#define PPSMC_MSG_PowerUpJpeg                    0x2C

#define PPSMC_MSG_PowerDownJpeg	                 0x2D



//Resets

#define PPSMC_MSG_PrepareMp1ForUnload            0x2E

#define PPSMC_MSG_Mode1Reset                     0x2F



//Set SystemVirtual DramAddrHigh

#define PPSMC_MSG_SetSystemVirtualDramAddrHigh   0x30

#define PPSMC_MSG_SetSystemVirtualDramAddrLow    0x31

//ACDC Power Source

#define PPSMC_MSG_SetPptLimit                    0x32

#define PPSMC_MSG_GetPptLimit                    0x33

#define PPSMC_MSG_ReenableAcDcInterrupt          0x34

#define PPSMC_MSG_NotifyPowerSource              0x35



//BTC

#define PPSMC_MSG_RunDcBtc                       0x36



//Debug

#define PPSMC_MSG_GetDebugData                   0x37



//Others

#define PPSMC_MSG_SetTemperatureInputSelect      0x38

#define PPSMC_MSG_SetFwDstatesMask               0x39

#define PPSMC_MSG_SetThrottlerMask               0x3A



#define PPSMC_MSG_SetExternalClientDfCstateAllow 0x3B



#define PPSMC_MSG_SetMGpuFanBoostLimitRpm        0x3C



//STB to dram log

#define PPSMC_MSG_DumpSTBtoDram                  0x3D

#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh    0x3E

#define PPSMC_MSG_STBtoDramLogSetDramAddrLow     0x3F

#define PPSMC_MSG_STBtoDramLogSetDramSize        0x40



#define PPSMC_MSG_SetGpoAllow                    0x41

#define PPSMC_MSG_AllowGfxDcs                    0x42

#define PPSMC_MSG_DisallowGfxDcs                 0x43

#define PPSMC_MSG_EnableAudioStutterWA           0x44

#define PPSMC_MSG_PowerUpUmsch                   0x45

#define PPSMC_MSG_PowerDownUmsch                 0x46

#define PPSMC_Message_Count                      0x47



//Debug Dump Message

#define DEBUGSMC_MSG_TestMessage                    0x1

#define DEBUGSMC_MSG_GetDebugData                   0x2

#define DEBUGSMC_MSG_DebugDumpExit                  0x3

#define DEBUGSMC_Message_Count                      0x4

#endif