Commit cf1f6877 authored by Dan Williams's avatar Dan Williams
Browse files

cxl/memdev: Add numa_node attribute



While CXL memory targets will have their own memory target node,
individual memory devices may be affinitized like other PCI devices.
Emit that attribute for memdevs.

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/164298428430.3018233.16409089892707993289.stgit@dwillia2-desk3.amr.corp.intel.com


Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent bcc79ea3
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+9 −0
Original line number Original line Diff line number Diff line
@@ -34,6 +34,15 @@ Description:
		capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
		capability. Mandatory for CXL devices, see CXL 2.0 8.1.12.2
		Memory Device PCIe Capabilities and Extended Capabilities.
		Memory Device PCIe Capabilities and Extended Capabilities.


What:		/sys/bus/cxl/devices/memX/numa_node
Date:		January, 2022
KernelVersion:	v5.18
Contact:	linux-cxl@vger.kernel.org
Description:
		(RO) If NUMA is enabled and the platform has affinitized the
		host PCI device for this memory device, emit the CPU node
		affinity for this device.

What:		/sys/bus/cxl/devices/*/devtype
What:		/sys/bus/cxl/devices/*/devtype
Date:		June, 2021
Date:		June, 2021
KernelVersion:	v5.14
KernelVersion:	v5.14
+17 −0
Original line number Original line Diff line number Diff line
@@ -99,11 +99,19 @@ static ssize_t serial_show(struct device *dev, struct device_attribute *attr,
}
}
static DEVICE_ATTR_RO(serial);
static DEVICE_ATTR_RO(serial);


static ssize_t numa_node_show(struct device *dev, struct device_attribute *attr,
			      char *buf)
{
	return sprintf(buf, "%d\n", dev_to_node(dev));
}
static DEVICE_ATTR_RO(numa_node);

static struct attribute *cxl_memdev_attributes[] = {
static struct attribute *cxl_memdev_attributes[] = {
	&dev_attr_serial.attr,
	&dev_attr_serial.attr,
	&dev_attr_firmware_version.attr,
	&dev_attr_firmware_version.attr,
	&dev_attr_payload_max.attr,
	&dev_attr_payload_max.attr,
	&dev_attr_label_storage_size.attr,
	&dev_attr_label_storage_size.attr,
	&dev_attr_numa_node.attr,
	NULL,
	NULL,
};
};


@@ -117,8 +125,17 @@ static struct attribute *cxl_memdev_ram_attributes[] = {
	NULL,
	NULL,
};
};


static umode_t cxl_memdev_visible(struct kobject *kobj, struct attribute *a,
				  int n)
{
	if (!IS_ENABLED(CONFIG_NUMA) && a == &dev_attr_numa_node.attr)
		return 0;
	return a->mode;
}

static struct attribute_group cxl_memdev_attribute_group = {
static struct attribute_group cxl_memdev_attribute_group = {
	.attrs = cxl_memdev_attributes,
	.attrs = cxl_memdev_attributes,
	.is_visible = cxl_memdev_visible,
};
};


static struct attribute_group cxl_memdev_ram_attribute_group = {
static struct attribute_group cxl_memdev_ram_attribute_group = {
+1 −0
Original line number Original line Diff line number Diff line
@@ -583,6 +583,7 @@ static __init int cxl_test_init(void)
		if (!pdev)
		if (!pdev)
			goto err_mem;
			goto err_mem;
		pdev->dev.parent = &port->dev;
		pdev->dev.parent = &port->dev;
		set_dev_node(&pdev->dev, i % 2);


		rc = platform_device_add(pdev);
		rc = platform_device_add(pdev);
		if (rc) {
		if (rc) {