Commit cfa1e7f8 authored by Duncan Ma's avatar Duncan Ma Committed by Alex Deucher
Browse files

drm/amd/display: Fix OTG H timing reset for dcn314 



[Why]
When ODM is enabled, H timing control register reset
to 0. Div mode manual field get overwritten causing
no display on certain modes for dcn314.

[How]
Use REG_UPDATE instead of REG_SET to set div_mode
field.

Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarDuncan Ma <duncan.ma@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 6ebdaf20

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_optc.c

+2 −1
Original line number Diff line number Diff line
@@ -98,7 +98,8 @@ static void optc314_set_odm_combine(struct timing_generator *optc, int *opp_id, 
	REG_UPDATE(OPTC_WIDTH_CONTROL,

			OPTC_SEGMENT_WIDTH, mpcc_hactive);



	REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

	REG_UPDATE(OTG_H_TIMING_CNTL,

			OTG_H_TIMING_DIV_MODE, opp_cnt - 1);

	optc1->opp_count = opp_cnt;

}