Commit d00b0fa9 authored by Boyuan Zhang's avatar Boyuan Zhang Committed by Alex Deucher
Browse files

drm/amdgpu: enable DPG mode for VCN3.0 



Enable DPG mode for VCN3.0 by updating related flag.

V2: update description.

Signed-off-by: default avatarBoyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: default avatarJames Zhu <james.zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 7055f4a3

drivers/gpu/drm/amd/amdgpu/nv.c

+1 −0
Original line number Diff line number Diff line
@@ -726,6 +726,7 @@ static int nv_common_early_init(void *handle) 
			AMD_CG_SUPPORT_IH_CG |

			AMD_CG_SUPPORT_MC_LS;

		adev->pg_flags = AMD_PG_SUPPORT_VCN |

			AMD_PG_SUPPORT_VCN_DPG |

			AMD_PG_SUPPORT_JPEG |

			AMD_PG_SUPPORT_ATHUB;

		adev->external_rev_id = adev->rev_id + 0x28;

drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c

+5 −2
Original line number Diff line number Diff line
@@ -254,7 +254,8 @@ static int vcn_v3_0_hw_init(void *handle) 


done:

	if (!r)

		DRM_INFO("VCN decode and encode initialized successfully.\n");

		DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",

			(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");



	return r;

}
@@ -278,7 +279,9 @@ static int vcn_v3_0_hw_fini(void *handle) 


		ring = &adev->vcn.inst[i].ring_dec;



		if (RREG32_SOC15(VCN, i, mmUVD_STATUS))

		if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||

			(adev->vcn.cur_state != AMD_PG_STATE_GATE &&

			RREG32_SOC15(VCN, i, mmUVD_STATUS)))

			vcn_v3_0_set_powergating_state(adev, AMD_PG_STATE_GATE);



		ring->sched.ready = false;