Commit d0274aba authored by Jacky Liao's avatar Jacky Liao Committed by Alex Deucher
Browse files

drm/amd/display: Add DSCL memory low power support 



[Why]
The DSCL memory blocks should be powered down when they're not in use.
This will reduce power consumption.

[How]
1. Write to DSCL_MEM_PWR_FORCE to put memory to shutdown when DSCL is not
   used.
2. Added a debug option to allow this behaviour to be turned off

Signed-off-by: default avatarJacky Liao <ziyu.liao@amd.com>
Reviewed-by: default avatarEric Yang <eric.yang2@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 99349a8a

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -422,6 +422,7 @@ union mem_low_power_enable_options { 
	struct {

		bool i2c: 1;

		bool dmcu: 1;

		bool dscl: 1;

		bool cm: 1;

		bool mpc: 1;

		bool optc: 1;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h

+8 −0
Original line number Diff line number Diff line
@@ -51,6 +51,8 @@ 
	SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\

	SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \

	SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \

	SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \

	SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \

	SRI(OTG_H_BLANK, DSCL, id), \

	SRI(OTG_V_BLANK, DSCL, id), \

	SRI(SCL_MODE, DSCL, id), \
@@ -252,6 +254,8 @@ 
	TF_SF(DSCL0_SCL_VERT_FILTER_INIT_BOT_C, SCL_V_INIT_INT_BOT_C, mask_sh),\

	TF_SF(DSCL0_SCL_MODE, SCL_CHROMA_COEF_MODE, mask_sh),\

	TF_SF(DSCL0_SCL_MODE, SCL_COEF_RAM_SELECT_CURRENT, mask_sh), \

	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh), \

	TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh), \

	TF_SF(CM0_CM_ICSC_CONTROL, CM_ICSC_MODE, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C11, mask_sh), \

	TF_SF(CM0_CM_ICSC_C11_C12, CM_ICSC_C12, mask_sh), \
@@ -536,6 +540,8 @@ 
	type SCL_V_INIT_INT_BOT_C; \

	type SCL_CHROMA_COEF_MODE; \

	type SCL_COEF_RAM_SELECT_CURRENT; \

	type LUT_MEM_PWR_FORCE; \

	type LUT_MEM_PWR_STATE; \

	type CM_GAMUT_REMAP_MODE; \

	type CM_GAMUT_REMAP_C11; \

	type CM_GAMUT_REMAP_C12; \
@@ -1096,6 +1102,8 @@ struct dcn_dpp_mask { 
	uint32_t DSCL_EXT_OVERSCAN_TOP_BOTTOM; \

	uint32_t OTG_H_BLANK; \

	uint32_t OTG_V_BLANK; \

	uint32_t DSCL_MEM_PWR_CTRL; \

	uint32_t DSCL_MEM_PWR_STATUS; \

	uint32_t SCL_MODE; \

	uint32_t LB_DATA_FORMAT; \

	uint32_t LB_MEMORY_CTRL; \

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c

+23 −1
Original line number Diff line number Diff line
@@ -198,6 +198,20 @@ static enum dscl_mode_sel dpp1_dscl_get_dscl_mode( 
	return DSCL_MODE_SCALING_420_YCBCR_ENABLE;

}



static void dpp1_power_on_dscl(

	struct dpp *dpp_base,

	bool power_on)

{

	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);



	if (dpp->tf_regs->DSCL_MEM_PWR_CTRL) {

		REG_UPDATE(DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, power_on ? 0 : 3);

		if (power_on)

			REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5);

	}

}





static void dpp1_dscl_set_lb(

	struct dcn10_dpp *dpp,

	const struct line_buffer_params *lb_params,
@@ -678,6 +692,11 @@ void dpp1_dscl_set_scaler_manual_scale( 


	dpp->scl_data = *scl_data;



	if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl) {

		if (dscl_mode != DSCL_MODE_DSCL_BYPASS)

			dpp1_power_on_dscl(dpp_base, true);

	}



	/* Autocal off */

	REG_SET_3(DSCL_AUTOCAL, 0,

		AUTOCAL_MODE, AUTOCAL_MODE_OFF,
@@ -697,8 +716,11 @@ void dpp1_dscl_set_scaler_manual_scale( 
	/* SCL mode */

	REG_UPDATE(SCL_MODE, DSCL_MODE, dscl_mode);



	if (dscl_mode == DSCL_MODE_DSCL_BYPASS)

	if (dscl_mode == DSCL_MODE_DSCL_BYPASS) {

		if (dpp_base->ctx->dc->debug.enable_mem_low_power.bits.dscl)

			dpp1_power_on_dscl(dpp_base, false);

		return;

	}



	/* LB */

	lb_config =  dpp1_dscl_find_lb_memory_config(dpp, scl_data);

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h

+2 −4
Original line number Diff line number Diff line
@@ -632,8 +632,7 @@ 
	type CUR0_PIX_INV_MODE; \

	type CUR0_PIXEL_ALPHA_MOD_EN; \

	type CUR0_ROM_EN;\

	type OBUF_MEM_PWR_FORCE;\

	type LUT_MEM_PWR_FORCE

	type OBUF_MEM_PWR_FORCE





struct dcn2_dpp_shift {
@@ -659,8 +658,7 @@ struct dcn2_dpp_mask { 
	uint32_t COLOR_KEYER_RED; \

	uint32_t COLOR_KEYER_GREEN; \

	uint32_t COLOR_KEYER_BLUE; \

	uint32_t OBUF_MEM_PWR_CTRL; \

	uint32_t DSCL_MEM_PWR_CTRL

	uint32_t OBUF_MEM_PWR_CTRL



#define DPP_DCN2_REG_VARIABLE_LIST_CM_APPEND \

	uint32_t CM_GAMUT_REMAP_B_C11_C12; \

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dpp.h

+4 −1
Original line number Diff line number Diff line
@@ -163,6 +163,8 @@ 
	SRI(CM_SHAPER_LUT_DATA, CM, id),\

	SRI(CM_MEM_PWR_CTRL2, CM, id), \

	SRI(CM_MEM_PWR_STATUS2, CM, id), \

	SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \

	SRI(DSCL_MEM_PWR_CTRL, DSCL, id), \

	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_B, CM, id),\

	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_G, CM, id),\

	SRI(CM_BLNDGAM_RAMA_START_SLOPE_CNTL_R, CM, id),\
@@ -342,7 +344,8 @@ 
	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \

	TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\

	TF_SF(DSCL0_OBUF_MEM_PWR_CTRL, OBUF_MEM_PWR_FORCE, mask_sh),\

	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh)

	TF_SF(DSCL0_DSCL_MEM_PWR_CTRL, LUT_MEM_PWR_FORCE, mask_sh),\

	TF_SF(DSCL0_DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, mask_sh)



#define DPP_REG_LIST_SH_MASK_DCN30_UPDATED(mask_sh)\

	TF_SF(CM0_CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, mask_sh), \