Commit d06a171e authored by Vidya Sagar's avatar Vidya Sagar Committed by Thierry Reding
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dt-bindings: Add Tegra234 PCIe clocks and resets 



Add the clocks and resets used by the PCIe hardware found on
Tegra234 SoCs.

Signed-off-by: default avatarVidya Sagar <vidyas@nvidia.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d978ab1a

include/dt-bindings/clock/tegra234-clock.h

+22 −0
Original line number Diff line number Diff line
@@ -130,8 +130,30 @@ 
#define TEGRA234_CLK_SYNC_I2S6			150U

/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */

#define TEGRA234_CLK_UARTA			155U

/** @brief output of gate CLK_ENB_PEX1_CORE_6 */

#define TEGRA234_CLK_PEX1_C6_CORE		161U

/** @brief output of gate CLK_ENB_PEX2_CORE_7 */

#define TEGRA234_CLK_PEX2_C7_CORE		171U

/** @brief output of gate CLK_ENB_PEX2_CORE_8 */

#define TEGRA234_CLK_PEX2_C8_CORE		172U

/** @brief output of gate CLK_ENB_PEX2_CORE_9 */

#define TEGRA234_CLK_PEX2_C9_CORE		173U

/** @brief output of gate CLK_ENB_PEX2_CORE_10 */

#define TEGRA234_CLK_PEX2_C10_CORE		187U

/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */

#define TEGRA234_CLK_SDMMC_LEGACY_TM		219U

/** @brief output of gate CLK_ENB_PEX0_CORE_0 */

#define TEGRA234_CLK_PEX0_C0_CORE		220U

/** @brief output of gate CLK_ENB_PEX0_CORE_1 */

#define TEGRA234_CLK_PEX0_C1_CORE		221U

/** @brief output of gate CLK_ENB_PEX0_CORE_2 */

#define TEGRA234_CLK_PEX0_C2_CORE		222U

/** @brief output of gate CLK_ENB_PEX0_CORE_3 */

#define TEGRA234_CLK_PEX0_C3_CORE		223U

/** @brief output of gate CLK_ENB_PEX0_CORE_4 */

#define TEGRA234_CLK_PEX0_C4_CORE		224U

/** @brief output of gate CLK_ENB_PEX1_CORE_5 */

#define TEGRA234_CLK_PEX1_C5_CORE		225U

/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */

#define TEGRA234_CLK_PLLC4			237U

/** @brief 32K input clock provided by PMIC */

include/dt-bindings/reset/tegra234-reset.h

+26 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */

/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */



#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H

#define DT_BINDINGS_RESET_TEGRA234_RESET_H
@@ -10,9 +10,18 @@ 
 * @brief Identifiers for Resets controllable by firmware

 * @{

 */

#define TEGRA234_RESET_PEX1_CORE_6		11U

#define TEGRA234_RESET_PEX1_CORE_6_APB		12U

#define TEGRA234_RESET_PEX1_COMMON_APB		13U

#define TEGRA234_RESET_PEX2_CORE_7		14U

#define TEGRA234_RESET_PEX2_CORE_7_APB		15U

#define TEGRA234_RESET_HDA			20U

#define TEGRA234_RESET_HDACODEC			21U

#define TEGRA234_RESET_I2C1			24U

#define TEGRA234_RESET_PEX2_CORE_8		25U

#define TEGRA234_RESET_PEX2_CORE_8_APB		26U

#define TEGRA234_RESET_PEX2_CORE_9		27U

#define TEGRA234_RESET_PEX2_CORE_9_APB		28U

#define TEGRA234_RESET_I2C2			29U

#define TEGRA234_RESET_I2C3			30U

#define TEGRA234_RESET_I2C4			31U
@@ -20,6 +29,9 @@ 
#define TEGRA234_RESET_I2C7			33U

#define TEGRA234_RESET_I2C8			34U

#define TEGRA234_RESET_I2C9			35U

#define TEGRA234_RESET_PEX2_CORE_10		56U

#define TEGRA234_RESET_PEX2_CORE_10_APB		57U

#define TEGRA234_RESET_PEX2_COMMON_APB		58U

#define TEGRA234_RESET_PWM1			68U

#define TEGRA234_RESET_PWM2			69U

#define TEGRA234_RESET_PWM3			70U
@@ -30,6 +42,19 @@ 
#define TEGRA234_RESET_PWM8			75U

#define TEGRA234_RESET_SDMMC4			85U

#define TEGRA234_RESET_UARTA			100U

#define TEGRA234_RESET_PEX0_CORE_0		116U

#define TEGRA234_RESET_PEX0_CORE_1		117U

#define TEGRA234_RESET_PEX0_CORE_2		118U

#define TEGRA234_RESET_PEX0_CORE_3		119U

#define TEGRA234_RESET_PEX0_CORE_4		120U

#define TEGRA234_RESET_PEX0_CORE_0_APB		121U

#define TEGRA234_RESET_PEX0_CORE_1_APB		122U

#define TEGRA234_RESET_PEX0_CORE_2_APB		123U

#define TEGRA234_RESET_PEX0_CORE_3_APB		124U

#define TEGRA234_RESET_PEX0_CORE_4_APB		125U

#define TEGRA234_RESET_PEX0_COMMON_APB		126U

#define TEGRA234_RESET_PEX1_CORE_5		129U

#define TEGRA234_RESET_PEX1_CORE_5_APB		130U



/** @} */