Commit d082a025 authored by Mark Brown's avatar Mark Brown Committed by Will Deacon
Browse files

arm64/mte: Add hwcap for asymmetric mode 



Allow userspace to detect support for asymmetric mode by providing a hwcap
for it, using the official feature name FEAT_MTE3.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Reviewed-by: default avatarVincenzo Frascino <Vincenzo.Frascino@arm.com>
Tested-by: default avatarBranislav Rankov <branislav.rankov@arm.com>
Link: https://lore.kernel.org/r/20220216173224.2342152-4-broonie@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent cb627397

Documentation/arm64/elf_hwcaps.rst

+5 −0
Original line number Diff line number Diff line
@@ -259,6 +259,11 @@ HWCAP2_RPRES 


    Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.



HWCAP2_MTE3



    Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described

    by Documentation/arm64/memory-tagging-extension.rst.



4. Unused AT_HWCAP bits

-----------------------

arch/arm64/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ 
#define KERNEL_HWCAP_ECV		__khwcap2_feature(ECV)

#define KERNEL_HWCAP_AFP		__khwcap2_feature(AFP)

#define KERNEL_HWCAP_RPRES		__khwcap2_feature(RPRES)

#define KERNEL_HWCAP_MTE3		__khwcap2_feature(MTE3)



/*

 * This yields a mask that user programs can use to figure out what

arch/arm64/include/uapi/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -78,5 +78,6 @@ 
#define HWCAP2_ECV		(1 << 19)

#define HWCAP2_AFP		(1 << 20)

#define HWCAP2_RPRES		(1 << 21)

#define HWCAP2_MTE3		(1 << 22)



#endif /* _UAPI__ASM_HWCAP_H */

arch/arm64/kernel/cpufeature.c

+1 −0
Original line number Diff line number Diff line
@@ -2488,6 +2488,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 
#endif

#ifdef CONFIG_ARM64_MTE

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),

	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),

#endif /* CONFIG_ARM64_MTE */

	HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),

	HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),

arch/arm64/kernel/cpuinfo.c

+1 −0
Original line number Diff line number Diff line
@@ -97,6 +97,7 @@ static const char *const hwcap_str[] = { 
	[KERNEL_HWCAP_ECV]		= "ecv",

	[KERNEL_HWCAP_AFP]		= "afp",

	[KERNEL_HWCAP_RPRES]		= "rpres",

	[KERNEL_HWCAP_MTE3]		= "mte3",

};



#ifdef CONFIG_COMPAT