Unverified Commit d2717584 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'ti-k3-dt-for-v5.18' of... 

Merge tag 'ti-k3-dt-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into arm/dt

TI K3 device tree updates for v5.18

Since (ti-k3-dt-fixes-for-v5.17):
Fixes:
* Cleanups for flash nodes across K3.
* gic-v3 backward compatible registers
* j721s2 interrupt parent fixup for wakeup GPIO

New:
* AM62 SoC and AM62-SK board
* wdt support for am64

* tag 'ti-k3-dt-for-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
  arm64: dts: ti: Add support for AM62-SK
  arm64: dts: ti: Introduce base support for AM62x SoC
  dt-bindings: pinctrl: k3: Introduce pinmux definitions for AM62
  dt-bindings: arm: ti: Add bindings for AM625 SoC
  arm64: dts: ti: k3-*: Drop address and size cells from flash nodes
  arm64: dts: ti: k3-*: Fix whitespace around flash@0 nodes
  arm64: dts: ti: k3-j721s2: Fix gic-v3 compatible regs
  arm64: dts: ti: k3-am64: Fix gic-v3 compatible regs
  arm64: dts: ti: k3-j7200: Fix gic-v3 compatible regs
  arm64: dts: ti: k3-j721e: Fix gic-v3 compatible regs
  arm64: dts: ti: k3-am65: Fix gic-v3 compatible regs
  arm64: dts: ti: k3-j721s2-mcu-wakeup: Fix the interrupt-parent for wkup_gpioX instances
  arm64: dts: ti: k3-am64: Add ESM0 to device memory map
  arm64: dts: ti: k3-am65*: Remove #address-cells/#size-cells from flash nodes
  arm64: dts: ti: k3-am64-main: Add RTI watchdog nodes
  arm64: dts: ti: k3-j721s2-common-proc-board: Alias console uart to serial2
  arm64: dts: ti: k3-j721s2: Move aliases to board dts

Link: https://lore.kernel.org/r/20220228120711.xdburehxs5gnwxko@capacity


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents bb67752b a033588e

Documentation/devicetree/bindings/arm/ti/k3.yaml

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@@ -46,6 +46,12 @@ properties: 
                  - ti,j7200-evm

              - const: ti,j7200



      - description: K3 AM625 SoC

        items:

          - enum:

              - ti,am625-sk

          - const: ti,am625



      - description: K3 AM642 SoC

        items:

          - enum:

arch/arm64/boot/dts/ti/Makefile

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@@ -21,3 +21,5 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb 


dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb

dtb-$(CONFIG_ARCH_K3) += k3-am642-sk.dtb



dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb

arch/arm64/boot/dts/ti/k3-am62-main.dtsi

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// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for AM625 SoC Family Main Domain peripherals

 *

 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/

 */



&cbass_main {

	gic500: interrupt-controller@1800000 {

		compatible = "arm,gic-v3";

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		#interrupt-cells = <3>;

		interrupt-controller;

		reg = <0x00 0x01800000 0x00 0x10000>,	/* GICD */

		      <0x00 0x01880000 0x00 0xc0000>,	/* GICR */

		      <0x00 0x01880000 0x00 0xc0000>,   /* GICR */

		      <0x01 0x00000000 0x00 0x2000>,    /* GICC */

		      <0x01 0x00010000 0x00 0x1000>,    /* GICH */

		      <0x01 0x00020000 0x00 0x2000>;    /* GICV */

		/*

		 * vcpumntirq:

		 * virtual CPU interface maintenance interrupt

		 */

		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;



		gic_its: msi-controller@1820000 {

			compatible = "arm,gic-v3-its";

			reg = <0x00 0x01820000 0x00 0x10000>;

			socionext,synquacer-pre-its = <0x1000000 0x400000>;

			msi-controller;

			#msi-cells = <1>;

		};

	};



	main_conf: syscon@100000 {

		compatible = "syscon", "simple-mfd";

		reg = <0x00 0x00100000 0x00 0x20000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x00 0x00100000 0x20000>;

	};



	dmss: bus@48000000 {

		compatible = "simple-mfd";

		#address-cells = <2>;

		#size-cells = <2>;

		dma-ranges;

		ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;



		ti,sci-dev-id = <25>;



		secure_proxy_main: mailbox@4d000000 {

			compatible = "ti,am654-secure-proxy";

			#mbox-cells = <1>;

			reg-names = "target_data", "rt", "scfg";

			reg = <0x00 0x4d000000 0x00 0x80000>,

			      <0x00 0x4a600000 0x00 0x80000>,

			      <0x00 0x4a400000 0x00 0x80000>;

			interrupt-names = "rx_012";

			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

		};

	};



	dmsc: system-controller@44043000 {

		compatible = "ti,k2g-sci";

		ti,host-id = <12>;

		mbox-names = "rx", "tx";

		mboxes= <&secure_proxy_main 12>,

			<&secure_proxy_main 13>;

		reg-names = "debug_messages";

		reg = <0x00 0x44043000 0x00 0xfe0>;



		k3_pds: power-controller {

			compatible = "ti,sci-pm-domain";

			#power-domain-cells = <2>;

		};



		k3_clks: clock-controller {

			compatible = "ti,k2g-sci-clk";

			#clock-cells = <2>;

		};



		k3_reset: reset-controller {

			compatible = "ti,sci-reset";

			#reset-cells = <2>;

		};

	};



	main_pmx0: pinctrl@f4000 {

		compatible = "pinctrl-single";

		reg = <0x00 0xf4000 0x00 0x2ac>;

		#pinctrl-cells = <1>;

		pinctrl-single,register-width = <32>;

		pinctrl-single,function-mask = <0xffffffff>;

	};



	main_uart0: serial@2800000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02800000 0x00 0x100>;

		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 146 0>;

		clock-names = "fclk";

	};



	main_uart1: serial@2810000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02810000 0x00 0x100>;

		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 152 0>;

		clock-names = "fclk";

	};



	main_uart2: serial@2820000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02820000 0x00 0x100>;

		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 153 0>;

		clock-names = "fclk";

	};



	main_uart3: serial@2830000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02830000 0x00 0x100>;

		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 154 0>;

		clock-names = "fclk";

	};



	main_uart4: serial@2840000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02840000 0x00 0x100>;

		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 155 0>;

		clock-names = "fclk";

	};



	main_uart5: serial@2850000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02850000 0x00 0x100>;

		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 156 0>;

		clock-names = "fclk";

	};



	main_uart6: serial@2860000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x02860000 0x00 0x100>;

		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 158 0>;

		clock-names = "fclk";

	};



	main_i2c0: i2c@20000000 {

		compatible = "ti,am64-i2c", "ti,omap4-i2c";

		reg = <0x00 0x20000000 0x00 0x100>;

		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 102 2>;

		clock-names = "fck";

	};



	main_i2c1: i2c@20010000 {

		compatible = "ti,am64-i2c", "ti,omap4-i2c";

		reg = <0x00 0x20010000 0x00 0x100>;

		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 103 2>;

		clock-names = "fck";

	};



	main_i2c2: i2c@20020000 {

		compatible = "ti,am64-i2c", "ti,omap4-i2c";

		reg = <0x00 0x20020000 0x00 0x100>;

		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 104 2>;

		clock-names = "fck";

	};



	main_i2c3: i2c@20030000 {

		compatible = "ti,am64-i2c", "ti,omap4-i2c";

		reg = <0x00 0x20030000 0x00 0x100>;

		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 105 2>;

		clock-names = "fck";

	};



	main_gpio_intr: interrupt-controller@a00000 {

		compatible = "ti,sci-intr";

		reg = <0x00 0x00a00000 0x00 0x800>;

		ti,intr-trigger-type = <1>;

		interrupt-controller;

		interrupt-parent = <&gic500>;

		#interrupt-cells = <1>;

		ti,sci = <&dmsc>;

		ti,sci-dev-id = <3>;

		ti,interrupt-ranges = <0 32 16>;

	};



	main_gpio0: gpio@600000 {

		compatible = "ti,am64-gpio", "ti,keystone-gpio";

		reg = <0x0 0x00600000 0x0 0x100>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-parent = <&main_gpio_intr>;

		interrupts = <190>, <191>, <192>,

			     <193>, <194>, <195>;

		interrupt-controller;

		#interrupt-cells = <2>;

		ti,ngpio = <87>;

		ti,davinci-gpio-unbanked = <0>;

		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 77 0>;

		clock-names = "gpio";

	};



	main_gpio1: gpio@601000 {

		compatible = "ti,am64-gpio", "ti,keystone-gpio";

		reg = <0x0 0x00601000 0x0 0x100>;

		gpio-controller;

		#gpio-cells = <2>;

		interrupt-parent = <&main_gpio_intr>;

		interrupts = <180>, <181>, <182>,

			     <183>, <184>, <185>;

		interrupt-controller;

		#interrupt-cells = <2>;

		ti,ngpio = <88>;

		ti,davinci-gpio-unbanked = <0>;

		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 78 0>;

		clock-names = "gpio";

	};



	hwspinlock: spinlock@2a000000 {

		compatible = "ti,am64-hwspinlock";

		reg = <0x00 0x2a000000 0x00 0x1000>;

		#hwlock-cells = <1>;

	};



	mailbox0_cluster0: mailbox@29000000 {

		compatible = "ti,am64-mailbox";

		reg = <0x00 0x29000000 0x00 0x200>;

		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;

		#mbox-cells = <1>;

		ti,mbox-num-users = <4>;

		ti,mbox-num-fifos = <16>;

	};

};

arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi

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// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for AM625 SoC Family MCU Domain peripherals

 *

 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/

 */



&cbass_mcu {

	mcu_pmx0: pinctrl@4084000 {

		compatible = "pinctrl-single";

		reg = <0x00 0x04084000 0x00 0x88>;

		#pinctrl-cells = <1>;

		pinctrl-single,register-width = <32>;

		pinctrl-single,function-mask = <0xffffffff>;

	};



	mcu_uart0: serial@4a00000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x04a00000 0x00 0x100>;

		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 149 0>;

		clock-names = "fclk";

	};



	mcu_i2c0: i2c@4900000 {

		compatible = "ti,am64-i2c", "ti,omap4-i2c";

		reg = <0x00 0x04900000 0x00 0x100>;

		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 106 2>;

		clock-names = "fck";

	};

};

arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi

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// SPDX-License-Identifier: GPL-2.0

/*

 * Device Tree Source for AM625 SoC Family Wakeup Domain peripherals

 *

 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/

 */



&cbass_wakeup {

	wkup_conf: syscon@43000000 {

		compatible = "syscon", "simple-mfd";

		reg = <0x00 0x43000000 0x00 0x20000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x00 0x43000000 0x20000>;



		chipid: chipid@14 {

			compatible = "ti,am654-chipid";

			reg = <0x14 0x4>;

		};

	};



	wkup_uart0: serial@2b300000 {

		compatible = "ti,am64-uart", "ti,am654-uart";

		reg = <0x00 0x2b300000 0x00 0x100>;

		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 114 0>;

		clock-names = "fclk";

	};



	wkup_i2c0: i2c@2b200000 {

		compatible = "ti,am64-i2c", "ti,omap4-i2c";

		reg = <0x00 0x02b200000 0x00 0x100>;

		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;

		#address-cells = <1>;

		#size-cells = <0>;

		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;

		clocks = <&k3_clks 107 4>;

		clock-names = "fck";

	};

};