Commit d2b0b483 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/pm: unify the interface for power gating 



No need to have special handling for swSMU supported ASICs.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d34a1ea9

drivers/gpu/drm/amd/pm/amdgpu_dpm.c

+0 −9
Original line number Original line Diff line number Diff line
@@ -927,7 +927,6 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block 
{

{

	int ret = 0;

	int ret = 0;

	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;

	const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;

	bool swsmu = is_support_sw_smu(adev);





	switch (block_type) {

	switch (block_type) {

	case AMD_IP_BLOCK_TYPE_UVD:

	case AMD_IP_BLOCK_TYPE_UVD:
@@ -968,15 +967,7 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block 
	case AMD_IP_BLOCK_TYPE_GFX:

	case AMD_IP_BLOCK_TYPE_GFX:

	case AMD_IP_BLOCK_TYPE_VCN:

	case AMD_IP_BLOCK_TYPE_VCN:

	case AMD_IP_BLOCK_TYPE_SDMA:

	case AMD_IP_BLOCK_TYPE_SDMA:

		if (pp_funcs && pp_funcs->set_powergating_by_smu) {

			ret = (pp_funcs->set_powergating_by_smu(

				(adev)->powerplay.pp_handle, block_type, gate));

		}

		break;

	case AMD_IP_BLOCK_TYPE_JPEG:

	case AMD_IP_BLOCK_TYPE_JPEG:

		if (swsmu)

			ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate);

		break;

	case AMD_IP_BLOCK_TYPE_GMC:

	case AMD_IP_BLOCK_TYPE_GMC:

	case AMD_IP_BLOCK_TYPE_ACP:

	case AMD_IP_BLOCK_TYPE_ACP:

		if (pp_funcs && pp_funcs->set_powergating_by_smu) {

		if (pp_funcs && pp_funcs->set_powergating_by_smu) {

drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h

+0 −3
Original line number Original line Diff line number Diff line
@@ -1270,9 +1270,6 @@ bool is_support_sw_smu(struct amdgpu_device *adev); 
bool is_support_cclk_dpm(struct amdgpu_device *adev);

bool is_support_cclk_dpm(struct amdgpu_device *adev);

int smu_write_watermarks_table(struct smu_context *smu);

int smu_write_watermarks_table(struct smu_context *smu);





/* smu to display interface */

extern int smu_dpm_set_power_gate(void *handle, uint32_t block_type, bool gate);



int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,

int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,

			   uint32_t *min, uint32_t *max);

			   uint32_t *min, uint32_t *max);

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+3 −3
Original line number Original line Diff line number Diff line
@@ -268,7 +268,7 @@ static int smu_dpm_set_jpeg_enable(struct smu_context *smu, 
 *    Under this case, the smu->mutex lock protection is already enforced on

 *    Under this case, the smu->mutex lock protection is already enforced on

 *    the parent API smu_force_performance_level of the call path.

 *    the parent API smu_force_performance_level of the call path.

 */

 */

int smu_dpm_set_power_gate(void *handle,

static int smu_dpm_set_power_gate(void *handle,

				  uint32_t block_type,

				  uint32_t block_type,

				  bool gate)

				  bool gate)

{

{