Commit d30c4ffc authored by Ken Sloat's avatar Ken Sloat Committed by Mauro Carvalho Chehab
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media: atmel-isc: Add support for BT656 with CRC decoding



The ISC driver currently supports ITU-R 601 encoding which
utilizes the external hsync and vsync signals. ITU-R 656
format removes the need for these pins by embedding the
sync pulses within the data packet.

To support this feature, enable necessary register bits
when this feature is enabled via device tree.

Signed-off-by: default avatarKen Sloat <ksloat@aampglobal.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent dea25533
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+2 −0
Original line number Diff line number Diff line
@@ -24,6 +24,8 @@
#define ISC_PFE_CFG0_HPOL_LOW   BIT(0)
#define ISC_PFE_CFG0_VPOL_LOW   BIT(1)
#define ISC_PFE_CFG0_PPOL_LOW   BIT(2)
#define ISC_PFE_CFG0_CCIR656    BIT(9)
#define ISC_PFE_CFG0_CCIR_CRC   BIT(10)

#define ISC_PFE_CFG0_MODE_PROGRESSIVE   (0x0 << 4)
#define ISC_PFE_CFG0_MODE_MASK          GENMASK(6, 4)
+6 −1
Original line number Diff line number Diff line
@@ -1095,7 +1095,8 @@ static int isc_configure(struct isc_device *isc)
	pfe_cfg0  |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
	mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
	       ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
	       ISC_PFE_CFG0_MODE_MASK;
	       ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
		   ISC_PFE_CFG0_CCIR656;

	regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);

@@ -2084,6 +2085,10 @@ static int isc_parse_dt(struct device *dev, struct isc_device *isc)
		if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_PPOL_LOW;

		if (v4l2_epn.bus_type == V4L2_MBUS_BT656)
			subdev_entity->pfe_cfg0 |= ISC_PFE_CFG0_CCIR_CRC |
					ISC_PFE_CFG0_CCIR656;

		subdev_entity->asd->match_type = V4L2_ASYNC_MATCH_FWNODE;
		subdev_entity->asd->match.fwnode =
			of_fwnode_handle(rem);