Commit d35d473c authored by Ralf Baechle's avatar Ralf Baechle
Browse files

[MIPS] Fix the crime against humanity that mipsIRQ.S is. 


    
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent fde3505c

arch/mips/mips-boards/atlas/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -16,5 +16,5 @@ 
# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.

#



obj-y			:= atlas_int.o atlas_setup.o

obj-y			:= atlas_int.o atlas-irq.o atlas_setup.o

obj-$(CONFIG_KGDB)	+= atlas_gdb.o

arch/mips/mips-boards/generic/mipsIRQ.S→arch/mips/mips-boards/atlas/atlas-irq.S

+5 −42
Original line number Diff line number Diff line
@@ -2,8 +2,6 @@ 
 * Carsten Langgaard, carstenl@mips.com

 * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.

 *

 * ########################################################################

 *

 *  This program is free software; you can distribute it and/or modify it

 *  under the terms of the GNU General Public License (Version 2) as

 *  published by the Free Software Foundation.
@@ -17,10 +15,7 @@ 
 *  with this program; if not, write to the Free Software Foundation, Inc.,

 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.

 *

 * ########################################################################

 *

 * Interrupt exception dispatch code.

 *

 */

#include <linux/config.h>
@@ -28,33 +23,9 @@ 
#include <asm/mipsregs.h>

#include <asm/regdef.h>

#include <asm/stackframe.h>



#ifdef CONFIG_MIPS_ATLAS

#include <asm/mips-boards/atlasint.h>

#define CASCADE_IRQ		MIPSCPU_INT_ATLAS

#define CASCADE_DISPATCH	atlas_hw0_irqdispatch

#endif

#ifdef CONFIG_MIPS_MALTA

#include <asm/mips-boards/maltaint.h>

#define CASCADE_IRQ		MIPSCPU_INT_I8259A

#define CASCADE_DISPATCH	malta_hw0_irqdispatch

#endif

#ifdef CONFIG_MIPS_SEAD

#include <asm/mips-boards/seadint.h>

#endif



/* A lot of complication here is taken away because:

 *

 * 1) We handle one interrupt and return, sitting in a loop and moving across

 *    all the pending IRQ bits in the cause register is _NOT_ the answer, the

 *    common case is one pending IRQ so optimize in that direction.

 *

 * 2) We need not check against bits in the status register IRQ mask, that

 *    would make this routine slow as hell.

 *

 * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in

 *    between like BSD spl() brain-damage.

 *

/*

 * Furthermore, the IRQs on the MIPS board look basically (barring software

 * IRQs which we don't use at all and all external interrupt sources are

 * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
@@ -127,31 +98,23 @@ 
	# sll	s0, t0

#endif



#ifdef CASCADE_IRQ

	 li	a1, CASCADE_IRQ

	 li	a1, MIPSCPU_INT_ATLAS

	bne	a0, a1, 1f

	 addu	a0, MIPSCPU_INT_BASE



	jal	CASCADE_DISPATCH

	jal	atlas_hw0_irqdispatch

	 move	 a0, sp



	j	ret_from_irq

	 nop

1:

#else

	 addu	a0, MIPSCPU_INT_BASE

#endif



	jal	do_IRQ

1:	jal	do_IRQ

	 move	a1, sp



	j	ret_from_irq

	 nop





spurious:

	jal	spurious_interrupt

	 nop

	j	ret_from_irq

	j	spurious_interrupt

	 nop

	END(mipsIRQ)

arch/mips/mips-boards/generic/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -18,8 +18,8 @@ 
# Makefile for the MIPS boards generic routines under Linux.

#



obj-y				:= mipsIRQ.o reset.o display.o init.o memory.o \

				   printf.o cmdline.o time.o

obj-y				:= reset.o display.o init.o memory.o printf.o \

				   cmdline.o time.o

obj-$(CONFIG_PCI)		+= pci.o

obj-$(CONFIG_KGDB)		+= gdb_hook.o

arch/mips/mips-boards/malta/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -19,4 +19,4 @@ 
# under Linux.

#



obj-y := malta_int.o malta_setup.o
 
obj-y := malta_int.o malta-irq.o malta_setup.o

arch/mips/mips-boards/malta/malta-irq.S

0 → 100644
+122 −0
Original line number Diff line number Diff line 
/*

 * Carsten Langgaard, carstenl@mips.com

 * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.

 *

 * ########################################################################

 *

 *  This program is free software; you can distribute it and/or modify it

 *  under the terms of the GNU General Public License (Version 2) as

 *  published by the Free Software Foundation.

 *

 *  This program is distributed in the hope it will be useful, but WITHOUT

 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

 *  for more details.

 *

 *  You should have received a copy of the GNU General Public License along

 *  with this program; if not, write to the Free Software Foundation, Inc.,

 *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.

 *

 * ########################################################################

 *

 * Interrupt exception dispatch code.

 *

 */

#include <linux/config.h>



#include <asm/asm.h>

#include <asm/mipsregs.h>

#include <asm/regdef.h>

#include <asm/stackframe.h>

#include <asm/mips-boards/maltaint.h>



/*

 * IRQs on the Malta board look basically (barring software IRQs which we

 * don't use at all and all external interrupt sources are combined together

 * on hardware interrupt 0 (MIPS IRQ 2)) like:

 *

 *	MIPS IRQ	Source

 *      --------        ------

 *             0	Software (ignored)

 *             1        Software (ignored)

 *             2        Combined hardware interrupt (hw0)

 *             3        Hardware (ignored)

 *             4        Hardware (ignored)

 *             5        Hardware (ignored)

 *             6        Hardware (ignored)

 *             7        R4k timer (what we use)

 *

 * We handle the IRQ according to _our_ priority which is:

 *

 * Highest ----     R4k Timer

 * Lowest  ----     Combined hardware interrupt

 *

 * then we just return, if multiple IRQs are pending then we will just take

 * another exception, big deal.

 */



	.text

	.set	noreorder

	.set	noat

	.align	5

	NESTED(mipsIRQ, PT_SIZE, sp)

	SAVE_ALL

	CLI

	.set	at



	mfc0	s0, CP0_CAUSE		# get irq bits

	mfc0	s1, CP0_STATUS		# get irq mask

	andi	s0, ST0_IM		# CAUSE.CE may be non-zero!

	and	s0, s1



#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)

 	.set	mips32

	clz	a0, s0

	.set	mips0

	negu	a0

	addu	a0, 31-CAUSEB_IP

	bltz	a0, spurious

#else

	beqz	s0, spurious

	 li	a0, 7



	and	t0, s0, 0xf000

	sltiu	t0, t0, 1

	sll	t0, 2

	subu	a0, t0

	sll	s0, t0



	and	t0, s0, 0xc000

	sltiu	t0, t0, 1

	sll	t0, 1

	subu	a0, t0

	sll	s0, t0



	and	t0, s0, 0x8000

	sltiu	t0, t0, 1

	# sll	t0, 0

	subu	a0, t0

	# sll	s0, t0

#endif



	 li	a1, MIPSCPU_INT_I8259A

	bne	a0, a1, 1f

	 addu	a0, MIPSCPU_INT_BASE



	jal	malta_hw0_irqdispatch

	 move	 a0, sp



	j	ret_from_irq

	 nop

1:



	jal	do_IRQ

	 move	a1, sp



	j	ret_from_irq

	 nop



spurious:

	j	spurious_interrupt

	 nop

	END(mipsIRQ)