Commit d386f645 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amdgpu: enable clock gating for HDP 6.0 



Enable HDP 6.0 clock gating.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 20139069

drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c

+71 −29
Original line number Diff line number Diff line
@@ -40,31 +40,83 @@ static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev, 
static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,

					 bool enable)

{

	uint32_t hdp_clk_cntl;

	uint32_t hdp_clk_cntl, hdp_clk_cntl1;

	uint32_t hdp_mem_pwr_cntl;



	if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))

	if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |

				AMD_CG_SUPPORT_HDP_DS |

				AMD_CG_SUPPORT_HDP_SD)))

		return;



	hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

	hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);

	hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);



	/* Before doing clock/power mode switch,

	 * forced on IPH & RC clock */

	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

				     RC_MEM_CLK_SOFT_OVERRIDE, 1);

	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);



	/* disable clock and power gating before any changing */

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 ATOMIC_MEM_POWER_CTRL_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 ATOMIC_MEM_POWER_LS_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 ATOMIC_MEM_POWER_DS_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 ATOMIC_MEM_POWER_SD_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 RC_MEM_POWER_CTRL_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 RC_MEM_POWER_LS_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 RC_MEM_POWER_DS_EN, 0);

	hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

					 RC_MEM_POWER_SD_EN, 0);

	WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);



	/* Already disabled above. The actions below are for "enabled" only */

	if (enable) {

		hdp_clk_cntl &=

			~(uint32_t)

			(HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

			 HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);

	} else {

		hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

			HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;

		/* only one clock gating mode (LS/DS/SD) can be enabled */

		if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 ATOMIC_MEM_POWER_SD_EN, 1);

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 RC_MEM_POWER_SD_EN, 1);

		} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 ATOMIC_MEM_POWER_LS_EN, 1);

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 RC_MEM_POWER_LS_EN, 1);

		} else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 ATOMIC_MEM_POWER_DS_EN, 1);

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,

							 HDP_MEM_POWER_CTRL,

							 RC_MEM_POWER_DS_EN, 1);

		}



		/* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to

		 * be set for SRAM LS/DS/SD */

		if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |

				      AMD_CG_SUPPORT_HDP_SD)) {

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

							 ATOMIC_MEM_POWER_CTRL_EN, 1);

			hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,

							 RC_MEM_POWER_CTRL_EN, 1);

			WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);

		}

	}



	/* disable IPH & RC clock override after clock/power mode changing */

	hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,

				     RC_MEM_CLK_SOFT_OVERRIDE, 0);

	WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);

}
@@ -73,16 +125,6 @@ static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev, 
{

	uint32_t tmp;



	/* AMD_CG_SUPPORT_HDP_MGCG */

	tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);

	if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |

		     HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))

		*flags |= AMD_CG_SUPPORT_HDP_MGCG;



	/* AMD_CG_SUPPORT_HDP_LS/DS/SD */

	tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);

	if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)

drivers/gpu/drm/amd/amdgpu/soc21.c

+2 −1
Original line number Diff line number Diff line
@@ -538,7 +538,8 @@ static int soc21_common_early_init(void *handle) 
			AMD_CG_SUPPORT_ATHUB_LS |

			AMD_CG_SUPPORT_MC_MGCG |

			AMD_CG_SUPPORT_MC_LS |

			AMD_CG_SUPPORT_IH_CG;

			AMD_CG_SUPPORT_IH_CG |

			AMD_CG_SUPPORT_HDP_SD;

		adev->pg_flags = AMD_PG_SUPPORT_VCN |

			AMD_PG_SUPPORT_VCN_DPG |

			AMD_PG_SUPPORT_JPEG |