Loading arch/arm/include/debug/brcmstb.S +16 −14 Original line number Diff line number Diff line Loading @@ -25,6 +25,7 @@ #define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000) #define UARTA_3390 REG_PHYS_ADDR(0x40a900) #define UARTA_72116 UARTA_7255 #define UARTA_7250 REG_PHYS_ADDR(0x40b400) #define UARTA_7255 REG_PHYS_ADDR(0x40c000) #define UARTA_7260 UARTA_7255 Loading Loading @@ -85,20 +86,21 @@ ARM_BE8( rev \rv, \rv ) /* Chip specific detection starts here */ 20: checkuart(\rp, \rv, 0x33900000, 3390) 21: checkuart(\rp, \rv, 0x72160000, 7216) 22: checkuart(\rp, \rv, 0x07216400, 72164) 23: checkuart(\rp, \rv, 0x07216500, 72165) 24: checkuart(\rp, \rv, 0x72500000, 7250) 25: checkuart(\rp, \rv, 0x72550000, 7255) 26: checkuart(\rp, \rv, 0x72600000, 7260) 27: checkuart(\rp, \rv, 0x72680000, 7268) 28: checkuart(\rp, \rv, 0x72710000, 7271) 29: checkuart(\rp, \rv, 0x72780000, 7278) 30: checkuart(\rp, \rv, 0x73640000, 7364) 31: checkuart(\rp, \rv, 0x73660000, 7366) 32: checkuart(\rp, \rv, 0x07437100, 74371) 33: checkuart(\rp, \rv, 0x74390000, 7439) 34: checkuart(\rp, \rv, 0x74450000, 7445) 21: checkuart(\rp, \rv, 0x07211600, 72116) 22: checkuart(\rp, \rv, 0x72160000, 7216) 23: checkuart(\rp, \rv, 0x07216400, 72164) 24: checkuart(\rp, \rv, 0x07216500, 72165) 25: checkuart(\rp, \rv, 0x72500000, 7250) 26: checkuart(\rp, \rv, 0x72550000, 7255) 27: checkuart(\rp, \rv, 0x72600000, 7260) 28: checkuart(\rp, \rv, 0x72680000, 7268) 29: checkuart(\rp, \rv, 0x72710000, 7271) 30: checkuart(\rp, \rv, 0x72780000, 7278) 31: checkuart(\rp, \rv, 0x73640000, 7364) 32: checkuart(\rp, \rv, 0x73660000, 7366) 33: checkuart(\rp, \rv, 0x07437100, 74371) 34: checkuart(\rp, \rv, 0x74390000, 7439) 35: checkuart(\rp, \rv, 0x74450000, 7445) /* No valid UART found */ 90: mov \rp, #0 Loading Loading
arch/arm/include/debug/brcmstb.S +16 −14 Original line number Diff line number Diff line Loading @@ -25,6 +25,7 @@ #define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000) #define UARTA_3390 REG_PHYS_ADDR(0x40a900) #define UARTA_72116 UARTA_7255 #define UARTA_7250 REG_PHYS_ADDR(0x40b400) #define UARTA_7255 REG_PHYS_ADDR(0x40c000) #define UARTA_7260 UARTA_7255 Loading Loading @@ -85,20 +86,21 @@ ARM_BE8( rev \rv, \rv ) /* Chip specific detection starts here */ 20: checkuart(\rp, \rv, 0x33900000, 3390) 21: checkuart(\rp, \rv, 0x72160000, 7216) 22: checkuart(\rp, \rv, 0x07216400, 72164) 23: checkuart(\rp, \rv, 0x07216500, 72165) 24: checkuart(\rp, \rv, 0x72500000, 7250) 25: checkuart(\rp, \rv, 0x72550000, 7255) 26: checkuart(\rp, \rv, 0x72600000, 7260) 27: checkuart(\rp, \rv, 0x72680000, 7268) 28: checkuart(\rp, \rv, 0x72710000, 7271) 29: checkuart(\rp, \rv, 0x72780000, 7278) 30: checkuart(\rp, \rv, 0x73640000, 7364) 31: checkuart(\rp, \rv, 0x73660000, 7366) 32: checkuart(\rp, \rv, 0x07437100, 74371) 33: checkuart(\rp, \rv, 0x74390000, 7439) 34: checkuart(\rp, \rv, 0x74450000, 7445) 21: checkuart(\rp, \rv, 0x07211600, 72116) 22: checkuart(\rp, \rv, 0x72160000, 7216) 23: checkuart(\rp, \rv, 0x07216400, 72164) 24: checkuart(\rp, \rv, 0x07216500, 72165) 25: checkuart(\rp, \rv, 0x72500000, 7250) 26: checkuart(\rp, \rv, 0x72550000, 7255) 27: checkuart(\rp, \rv, 0x72600000, 7260) 28: checkuart(\rp, \rv, 0x72680000, 7268) 29: checkuart(\rp, \rv, 0x72710000, 7271) 30: checkuart(\rp, \rv, 0x72780000, 7278) 31: checkuart(\rp, \rv, 0x73640000, 7364) 32: checkuart(\rp, \rv, 0x73660000, 7366) 33: checkuart(\rp, \rv, 0x07437100, 74371) 34: checkuart(\rp, \rv, 0x74390000, 7439) 35: checkuart(\rp, \rv, 0x74450000, 7445) /* No valid UART found */ 90: mov \rp, #0 Loading