Commit d631b984 authored by Anshuman Gupta's avatar Anshuman Gupta
Browse files

drm/i915/hdcp: Add HDCP 2.2 stream register 



Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.

B.Spec: 21780
B.Spec: 14410
B.Spec: 50573

v2
- Modified naming convention of HDCP2_STREAM_STATUS
  for pre-gen12 platforms inline with B.Spec.

Cc: Ramalingam C <ramalingam.c@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Reviewed-by: default avatarRamalingam C <ramalingam.c@intel.com>
Tested-by: default avatarKarthik B S <karthik.b.s@intel.com>
Signed-off-by: default avatarAnshuman Gupta <anshuman.gupta@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111081120.28417-17-anshuman.gupta@intel.com
parent 5bd29e32

drivers/gpu/drm/i915/i915_reg.h

+39 −0
Original line number Diff line number Diff line
@@ -9872,6 +9872,7 @@ enum skl_power_gate { 
					  _PORTD_HDCP2_BASE, \

					  _PORTE_HDCP2_BASE, \

					  _PORTF_HDCP2_BASE) + (x))



#define PORT_HDCP2_AUTH(port)		_PORT_HDCP2_BASE(port, 0x98)

#define _TRANSA_HDCP2_AUTH		0x66498

#define _TRANSB_HDCP2_AUTH		0x66598
@@ -9911,6 +9912,44 @@ enum skl_power_gate { 
					 TRANS_HDCP2_STATUS(trans) : \

					 PORT_HDCP2_STATUS(port))



#define _PIPEA_HDCP2_STREAM_STATUS	0x668C0

#define _PIPEB_HDCP2_STREAM_STATUS	0x665C0

#define _PIPEC_HDCP2_STREAM_STATUS	0x666C0

#define _PIPED_HDCP2_STREAM_STATUS	0x667C0

#define PIPE_HDCP2_STREAM_STATUS(pipe)		_MMIO(_PICK((pipe), \

						      _PIPEA_HDCP2_STREAM_STATUS, \

						      _PIPEB_HDCP2_STREAM_STATUS, \

						      _PIPEC_HDCP2_STREAM_STATUS, \

						      _PIPED_HDCP2_STREAM_STATUS))



#define _TRANSA_HDCP2_STREAM_STATUS		0x664C0

#define _TRANSB_HDCP2_STREAM_STATUS		0x665C0

#define TRANS_HDCP2_STREAM_STATUS(trans)	_MMIO_TRANS(trans, \

						    _TRANSA_HDCP2_STREAM_STATUS, \

						    _TRANSB_HDCP2_STREAM_STATUS)

#define   STREAM_ENCRYPTION_STATUS	BIT(31)

#define   STREAM_TYPE_STATUS		BIT(30)

#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \

					(INTEL_GEN(dev_priv) >= 12 ? \

					 TRANS_HDCP2_STREAM_STATUS(trans) : \

					 PIPE_HDCP2_STREAM_STATUS(pipe))



#define _PORTA_HDCP2_AUTH_STREAM		0x66F00

#define _PORTB_HDCP2_AUTH_STREAM		0x66F04

#define PORT_HDCP2_AUTH_STREAM(port)	_MMIO_PORT(port, \

						   _PORTA_HDCP2_AUTH_STREAM, \

						   _PORTB_HDCP2_AUTH_STREAM)

#define _TRANSA_HDCP2_AUTH_STREAM		0x66F00

#define _TRANSB_HDCP2_AUTH_STREAM		0x66F04

#define TRANS_HDCP2_AUTH_STREAM(trans)	_MMIO_TRANS(trans, \

						    _TRANSA_HDCP2_AUTH_STREAM, \

						    _TRANSB_HDCP2_AUTH_STREAM)

#define   AUTH_STREAM_TYPE		BIT(31)

#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \

					(INTEL_GEN(dev_priv) >= 12 ? \

					 TRANS_HDCP2_AUTH_STREAM(trans) : \

					 PORT_HDCP2_AUTH_STREAM(port))



/* Per-pipe DDI Function Control */

#define _TRANS_DDI_FUNC_CTL_A		0x60400

#define _TRANS_DDI_FUNC_CTL_B		0x61400