Commit d798f2f2 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/radeon/dce8: properly handle interlaced timing 



The register bits changed on DCE8 compared to previous
families.

Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9e05fa1d

drivers/gpu/drm/radeon/atombios_encoders.c

+7 −1
Original line number Diff line number Diff line
@@ -1962,7 +1962,13 @@ atombios_apply_encoder_quirks(struct drm_encoder *encoder, 
	/* set scaler clears this on some chips */

	if (ASIC_IS_AVIVO(rdev) &&

	    (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {

		if (ASIC_IS_DCE4(rdev)) {

		if (ASIC_IS_DCE8(rdev)) {

			if (mode->flags & DRM_MODE_FLAG_INTERLACE)

				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,

				       CIK_INTERLEAVE_EN);

			else

				WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);

		} else if (ASIC_IS_DCE4(rdev)) {

			if (mode->flags & DRM_MODE_FLAG_INTERLACE)

				WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,

				       EVERGREEN_INTERLEAVE_EN);

drivers/gpu/drm/radeon/cik_reg.h

+3 −0
Original line number Diff line number Diff line
@@ -62,4 +62,7 @@ 
#define CIK_ALPHA_CONTROL                         0x6af0

#       define CIK_CURSOR_ALPHA_BLND_ENA          (1 << 1)



#define CIK_LB_DATA_FORMAT                        0x6b00

#       define CIK_INTERLEAVE_EN                  (1 << 3)



#endif