Commit d8b2feb9 authored by Tony Lindgren's avatar Tony Lindgren
Browse files

ARM: OMAP2+: Drop unused CM and SCRM defines for omap4 



These are unused and should be handled by drivers/clock/ti nowadays.

Note that we also drop some unused SCRM registers that are not clock
related.

Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
parent 614c5589

arch/arm/mach-omap2/cm-regbits-44xx.h

+0 −101
Original line number Diff line number Diff line
@@ -20,71 +20,11 @@ 
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H



#define OMAP4430_ABE_STATDEP_SHIFT				3

#define OMAP4430_AUTO_DPLL_MODE_MASK				(0x7 << 0)

#define OMAP4430_CLKSEL_SHIFT					24

#define OMAP4430_CLKSEL_WIDTH					0x1

#define OMAP4430_CLKSEL_MASK					(1 << 24)

#define OMAP4430_CLKSEL_0_0_SHIFT				0

#define OMAP4430_CLKSEL_0_0_WIDTH				0x1

#define OMAP4430_CLKSEL_0_1_SHIFT				0

#define OMAP4430_CLKSEL_0_1_WIDTH				0x2

#define OMAP4430_CLKSEL_24_25_SHIFT				24

#define OMAP4430_CLKSEL_24_25_WIDTH				0x2

#define OMAP4430_CLKSEL_60M_SHIFT				24

#define OMAP4430_CLKSEL_60M_WIDTH				0x1

#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT				24

#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH				0x1

#define OMAP4430_CLKSEL_CORE_SHIFT				0

#define OMAP4430_CLKSEL_CORE_WIDTH				0x1

#define OMAP4430_CLKSEL_DIV_SHIFT				24

#define OMAP4430_CLKSEL_DIV_WIDTH				0x1

#define OMAP4430_CLKSEL_FCLK_SHIFT				24

#define OMAP4430_CLKSEL_FCLK_WIDTH				0x2

#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT			25

#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH			0x1

#define OMAP4430_CLKSEL_L3_SHIFT				4

#define OMAP4430_CLKSEL_L3_WIDTH				0x1

#define OMAP4430_CLKSEL_L4_SHIFT				8

#define OMAP4430_CLKSEL_L4_WIDTH				0x1

#define OMAP4430_CLKSEL_OPP_SHIFT				0

#define OMAP4430_CLKSEL_OPP_WIDTH				0x2

#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT			27

#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH			0x3

#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK			(0x7 << 24)

#define OMAP4430_CLKSEL_SGX_FCLK_MASK				(1 << 24)

#define OMAP4430_CLKSEL_SOURCE_MASK				(0x3 << 24)

#define OMAP4430_CLKSEL_SOURCE_24_24_MASK			(1 << 24)

#define OMAP4430_CLKSEL_UTMI_P1_SHIFT				24

#define OMAP4430_CLKSEL_UTMI_P1_WIDTH				0x1

#define OMAP4430_CLKSEL_UTMI_P2_SHIFT				25

#define OMAP4430_CLKSEL_UTMI_P2_WIDTH				0x1

#define OMAP4430_CLKTRCTRL_SHIFT				0

#define OMAP4430_CLKTRCTRL_MASK					(0x3 << 0)

#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT				23

#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH				0x1

#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK			(0x1f << 0)

#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT			8

#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK			(1 << 10)

#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT				0

#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH				0x5

#define OMAP4430_DPLL_CLKOUT_DIV_MASK				(0x1f << 0)

#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK			(0x7f << 0)

#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK			(1 << 8)

#define OMAP4430_DPLL_DIV_MASK					(0x7f << 0)

#define OMAP4430_DPLL_DIV_0_7_MASK				(0xff << 0)

#define OMAP4430_DPLL_EN_MASK					(0x7 << 0)

#define OMAP4430_DPLL_LPMODE_EN_MASK				(1 << 10)

#define OMAP4430_DPLL_MULT_MASK					(0x7ff << 8)

#define OMAP4430_DPLL_MULT_USB_MASK				(0xfff << 8)

#define OMAP4430_DPLL_REGM4XEN_MASK				(1 << 11)

#define OMAP4430_DPLL_SD_DIV_MASK				(0xff << 24)

#define OMAP4430_DSS_STATDEP_SHIFT				8

#define OMAP4430_DUCATI_STATDEP_SHIFT				0

#define OMAP4430_GFX_STATDEP_SHIFT				10

#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK			(0x1f << 0)

#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK			(0x1f << 0)

#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK			(0x1f << 0)

#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK			(0x1f << 0)

#define OMAP4430_IDLEST_SHIFT					16

#define OMAP4430_IDLEST_MASK					(0x3 << 16)

#define OMAP4430_IVAHD_STATDEP_SHIFT				2
@@ -98,46 +38,5 @@ 
#define OMAP4430_MEMIF_STATDEP_SHIFT				4

#define OMAP4430_MODULEMODE_SHIFT				0

#define OMAP4430_MODULEMODE_MASK				(0x3 << 0)

#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT			9

#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT			8

#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT				8

#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT			8

#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT				8

#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT				8

#define OMAP4430_OPTFCLKEN_FCLK_SHIFT				8

#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT				8

#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT				9

#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT				10

#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT			15

#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT		13

#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT		14

#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT			11

#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT			12

#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT			8

#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT		9

#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT			8

#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT			10

#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT		11

#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT			10

#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT			8

#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT				11

#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT			8

#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT			9

#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT			10

#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT			8

#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT			9

#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT			10

#define OMAP4430_OPTFCLKEN_XCLK_SHIFT				8

#define OMAP4430_PAD_CLKS_GATE_SHIFT				8

#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT				20

#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH				0x2

#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT			22

#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH			0x2

#define OMAP4430_SCALE_FCLK_SHIFT				0

#define OMAP4430_SCALE_FCLK_WIDTH				0x1

#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT				10

#define OMAP4430_ST_DPLL_CLK_MASK				(1 << 0)

#define OMAP4430_SYS_CLKSEL_SHIFT				0

#define OMAP4430_SYS_CLKSEL_WIDTH				0x3

#define OMAP4430_TESLA_STATDEP_SHIFT				1

#endif

arch/arm/mach-omap2/cm1_44xx.h

+0 −174
Original line number Diff line number Diff line
@@ -34,184 +34,10 @@ 
#define OMAP4430_CM1_MPU_INST		0x0300

#define OMAP4430_CM1_TESLA_INST		0x0400

#define OMAP4430_CM1_ABE_INST		0x0500

#define OMAP4430_CM1_RESTORE_INST	0x0e00

#define OMAP4430_CM1_INSTR_INST		0x0f00



/* CM1 clockdomain register offsets (from instance start) */

#define OMAP4430_CM1_MPU_MPU_CDOFFS	0x0000

#define OMAP4430_CM1_TESLA_TESLA_CDOFFS	0x0000

#define OMAP4430_CM1_ABE_ABE_CDOFFS	0x0000



/* CM1 */



/* CM1.OCP_SOCKET_CM1 register offsets */

#define OMAP4_REVISION_CM1_OFFSET			0x0000

#define OMAP4430_REVISION_CM1				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)

#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET		0x0040

#define OMAP4430_CM_CM1_PROFILING_CLKCTRL		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)



/* CM1.CKGEN_CM1 register offsets */

#define OMAP4_CM_CLKSEL_CORE_OFFSET			0x0000

#define OMAP4430_CM_CLKSEL_CORE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)

#define OMAP4_CM_CLKSEL_ABE_OFFSET			0x0008

#define OMAP4430_CM_CLKSEL_ABE				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)

#define OMAP4_CM_DLL_CTRL_OFFSET			0x0010

#define OMAP4430_CM_DLL_CTRL				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)

#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET		0x0020

#define OMAP4430_CM_CLKMODE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)

#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET		0x0024

#define OMAP4430_CM_IDLEST_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)

#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET		0x0028

#define OMAP4430_CM_AUTOIDLE_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)

#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET		0x002c

#define OMAP4430_CM_CLKSEL_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)

#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET		0x0030

#define OMAP4430_CM_DIV_M2_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)

#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET		0x0034

#define OMAP4430_CM_DIV_M3_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)

#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET		0x0038

#define OMAP4430_CM_DIV_M4_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)

#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET		0x003c

#define OMAP4430_CM_DIV_M5_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)

#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET		0x0040

#define OMAP4430_CM_DIV_M6_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)

#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET		0x0044

#define OMAP4430_CM_DIV_M7_DPLL_CORE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET	0x0048

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET	0x004c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)

#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET		0x0050

#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)

#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET		0x0060

#define OMAP4430_CM_CLKMODE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)

#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET			0x0064

#define OMAP4430_CM_IDLEST_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)

#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET		0x0068

#define OMAP4430_CM_AUTOIDLE_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)

#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET			0x006c

#define OMAP4430_CM_CLKSEL_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)

#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET			0x0070

#define OMAP4430_CM_DIV_M2_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET		0x0088

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET		0x008c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)

#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET			0x009c

#define OMAP4430_CM_BYPCLK_DPLL_MPU			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)

#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET		0x00a0

#define OMAP4430_CM_CLKMODE_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)

#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET			0x00a4

#define OMAP4430_CM_IDLEST_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)

#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET		0x00a8

#define OMAP4430_CM_AUTOIDLE_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)

#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET			0x00ac

#define OMAP4430_CM_CLKSEL_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)

#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET			0x00b8

#define OMAP4430_CM_DIV_M4_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)

#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET			0x00bc

#define OMAP4430_CM_DIV_M5_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET		0x00c8

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET		0x00cc

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)

#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET			0x00dc

#define OMAP4430_CM_BYPCLK_DPLL_IVA			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)

#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET		0x00e0

#define OMAP4430_CM_CLKMODE_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)

#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET			0x00e4

#define OMAP4430_CM_IDLEST_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)

#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET		0x00e8

#define OMAP4430_CM_AUTOIDLE_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)

#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET			0x00ec

#define OMAP4430_CM_CLKSEL_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)

#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET			0x00f0

#define OMAP4430_CM_DIV_M2_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)

#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET			0x00f4

#define OMAP4430_CM_DIV_M3_DPLL_ABE			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET		0x0108

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET		0x010c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)

#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET		0x0120

#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)

#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET		0x0124

#define OMAP4430_CM_IDLEST_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)

#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET		0x0128

#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)

#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET		0x012c

#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)

#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET		0x0130

#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)

#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET		0x0138

#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)

#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET		0x013c

#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)

#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET		0x0140

#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)

#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET	0x0148

#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)

#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET	0x014c

#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)

#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET		0x0160

#define OMAP4430_CM_SHADOW_FREQ_CONFIG1			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)

#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET		0x0164

#define OMAP4430_CM_SHADOW_FREQ_CONFIG2			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)

#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET			0x0170

#define OMAP4430_CM_DYN_DEP_PRESCAL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)

#define OMAP4_CM_RESTORE_ST_OFFSET			0x0180

#define OMAP4430_CM_RESTORE_ST				OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)



/* CM1.MPU_CM1 register offsets */

#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET			0x0000

#define OMAP4430_CM_MPU_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)

#define OMAP4_CM_MPU_STATICDEP_OFFSET			0x0004

#define OMAP4430_CM_MPU_STATICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)

#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET			0x0008

#define OMAP4430_CM_MPU_DYNAMICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)

#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET			0x0020

#define OMAP4430_CM_MPU_MPU_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)



/* CM1.TESLA_CM1 register offsets */

#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET			0x0000

#define OMAP4430_CM_TESLA_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)

#define OMAP4_CM_TESLA_STATICDEP_OFFSET			0x0004

#define OMAP4430_CM_TESLA_STATICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)

#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET		0x0008

#define OMAP4430_CM_TESLA_DYNAMICDEP			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)

#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET		0x0020

#define OMAP4430_CM_TESLA_TESLA_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)



/* CM1.ABE_CM1 register offsets */

#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET			0x0000

#define OMAP4430_CM1_ABE_CLKSTCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)

#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET		0x0020

#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)

#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET		0x0028

#define OMAP4430_CM1_ABE_AESS_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)

#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET		0x0030

#define OMAP4430_CM1_ABE_PDM_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)

#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET		0x0038

#define OMAP4430_CM1_ABE_DMIC_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)

#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET		0x0040

#define OMAP4430_CM1_ABE_MCASP_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)

#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET		0x0048

#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)

#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET		0x0050

#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)

#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET		0x0058

#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)

#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET		0x0060

#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL		OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)

#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET		0x0068

#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)

#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET		0x0070

#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)

#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET		0x0078

#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)

#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET		0x0080

#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)

#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET		0x0088

#define OMAP4430_CM1_ABE_WDT3_CLKCTRL			OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)



#endif

arch/arm/mach-omap2/cm2_44xx.h

+0 −386

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arch/arm/mach-omap2/scrm44xx.h

+0 −141
Original line number Diff line number Diff line
@@ -22,72 +22,7 @@ 
		OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))



/* Registers offset */

#define OMAP4_SCRM_REVISION_SCRM_OFFSET		0x0000

#define OMAP4_SCRM_REVISION_SCRM		OMAP44XX_SCRM_REGADDR(0x0000)

#define OMAP4_SCRM_CLKSETUPTIME_OFFSET		0x0100

#define OMAP4_SCRM_CLKSETUPTIME			OMAP44XX_SCRM_REGADDR(0x0100)

#define OMAP4_SCRM_PMICSETUPTIME_OFFSET		0x0104

#define OMAP4_SCRM_PMICSETUPTIME		OMAP44XX_SCRM_REGADDR(0x0104)

#define OMAP4_SCRM_ALTCLKSRC_OFFSET		0x0110

#define OMAP4_SCRM_ALTCLKSRC			OMAP44XX_SCRM_REGADDR(0x0110)

#define OMAP4_SCRM_MODEMCLKM_OFFSET		0x0118

#define OMAP4_SCRM_MODEMCLKM			OMAP44XX_SCRM_REGADDR(0x0118)

#define OMAP4_SCRM_D2DCLKM_OFFSET		0x011c

#define OMAP4_SCRM_D2DCLKM			OMAP44XX_SCRM_REGADDR(0x011c)

#define OMAP4_SCRM_EXTCLKREQ_OFFSET		0x0200

#define OMAP4_SCRM_EXTCLKREQ			OMAP44XX_SCRM_REGADDR(0x0200)

#define OMAP4_SCRM_ACCCLKREQ_OFFSET		0x0204

#define OMAP4_SCRM_ACCCLKREQ			OMAP44XX_SCRM_REGADDR(0x0204)

#define OMAP4_SCRM_PWRREQ_OFFSET		0x0208

#define OMAP4_SCRM_PWRREQ			OMAP44XX_SCRM_REGADDR(0x0208)

#define OMAP4_SCRM_AUXCLKREQ0_OFFSET		0x0210

#define OMAP4_SCRM_AUXCLKREQ0			OMAP44XX_SCRM_REGADDR(0x0210)

#define OMAP4_SCRM_AUXCLKREQ1_OFFSET		0x0214

#define OMAP4_SCRM_AUXCLKREQ1			OMAP44XX_SCRM_REGADDR(0x0214)

#define OMAP4_SCRM_AUXCLKREQ2_OFFSET		0x0218

#define OMAP4_SCRM_AUXCLKREQ2			OMAP44XX_SCRM_REGADDR(0x0218)

#define OMAP4_SCRM_AUXCLKREQ3_OFFSET		0x021c

#define OMAP4_SCRM_AUXCLKREQ3			OMAP44XX_SCRM_REGADDR(0x021c)

#define OMAP4_SCRM_AUXCLKREQ4_OFFSET		0x0220

#define OMAP4_SCRM_AUXCLKREQ4			OMAP44XX_SCRM_REGADDR(0x0220)

#define OMAP4_SCRM_AUXCLKREQ5_OFFSET		0x0224

#define OMAP4_SCRM_AUXCLKREQ5			OMAP44XX_SCRM_REGADDR(0x0224)

#define OMAP4_SCRM_D2DCLKREQ_OFFSET		0x0234

#define OMAP4_SCRM_D2DCLKREQ			OMAP44XX_SCRM_REGADDR(0x0234)

#define OMAP4_SCRM_AUXCLK0_OFFSET		0x0310

#define OMAP4_SCRM_AUXCLK0			OMAP44XX_SCRM_REGADDR(0x0310)

#define OMAP4_SCRM_AUXCLK1_OFFSET		0x0314

#define OMAP4_SCRM_AUXCLK1			OMAP44XX_SCRM_REGADDR(0x0314)

#define OMAP4_SCRM_AUXCLK2_OFFSET		0x0318

#define OMAP4_SCRM_AUXCLK2			OMAP44XX_SCRM_REGADDR(0x0318)

#define OMAP4_SCRM_AUXCLK3_OFFSET		0x031c

#define OMAP4_SCRM_AUXCLK3			OMAP44XX_SCRM_REGADDR(0x031c)

#define OMAP4_SCRM_AUXCLK4_OFFSET		0x0320

#define OMAP4_SCRM_AUXCLK4			OMAP44XX_SCRM_REGADDR(0x0320)

#define OMAP4_SCRM_AUXCLK5_OFFSET		0x0324

#define OMAP4_SCRM_AUXCLK5			OMAP44XX_SCRM_REGADDR(0x0324)

#define OMAP4_SCRM_RSTTIME_OFFSET		0x0400

#define OMAP4_SCRM_RSTTIME			OMAP44XX_SCRM_REGADDR(0x0400)

#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET		0x0418

#define OMAP4_SCRM_MODEMRSTCTRL			OMAP44XX_SCRM_REGADDR(0x0418)

#define OMAP4_SCRM_D2DRSTCTRL_OFFSET		0x041c

#define OMAP4_SCRM_D2DRSTCTRL			OMAP44XX_SCRM_REGADDR(0x041c)

#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET	0x0420

#define OMAP4_SCRM_EXTPWRONRSTCTRL		OMAP44XX_SCRM_REGADDR(0x0420)

#define OMAP4_SCRM_EXTWARMRSTST_OFFSET		0x0510

#define OMAP4_SCRM_EXTWARMRSTST			OMAP44XX_SCRM_REGADDR(0x0510)

#define OMAP4_SCRM_APEWARMRSTST_OFFSET		0x0514

#define OMAP4_SCRM_APEWARMRSTST			OMAP44XX_SCRM_REGADDR(0x0514)

#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET	0x0518

#define OMAP4_SCRM_MODEMWARMRSTST		OMAP44XX_SCRM_REGADDR(0x0518)

#define OMAP4_SCRM_D2DWARMRSTST_OFFSET		0x051c

#define OMAP4_SCRM_D2DWARMRSTST			OMAP44XX_SCRM_REGADDR(0x051c)



/* Registers shifts and masks */



/* REVISION_SCRM */

#define OMAP4_REV_SHIFT				0

#define OMAP4_REV_MASK				(0xff << 0)



/* CLKSETUPTIME */

#define OMAP4_DOWNTIME_SHIFT			16
@@ -95,80 +30,4 @@ 
#define OMAP4_SETUPTIME_SHIFT			0

#define OMAP4_SETUPTIME_MASK			(0xfff << 0)



/* PMICSETUPTIME */

#define OMAP4_WAKEUPTIME_SHIFT			16

#define OMAP4_WAKEUPTIME_MASK			(0x3f << 16)

#define OMAP4_SLEEPTIME_SHIFT			0

#define OMAP4_SLEEPTIME_MASK			(0x3f << 0)



/* ALTCLKSRC */

#define OMAP4_ENABLE_EXT_SHIFT			3

#define OMAP4_ENABLE_EXT_MASK			(1 << 3)

#define OMAP4_ENABLE_INT_SHIFT			2

#define OMAP4_ENABLE_INT_MASK			(1 << 2)

#define OMAP4_ALTCLKSRC_MODE_SHIFT		0

#define OMAP4_ALTCLKSRC_MODE_MASK		(0x3 << 0)



/* MODEMCLKM */

#define OMAP4_CLK_32KHZ_SHIFT			0

#define OMAP4_CLK_32KHZ_MASK			(1 << 0)



/* D2DCLKM */

#define OMAP4_SYSCLK_SHIFT			1

#define OMAP4_SYSCLK_MASK			(1 << 1)



/* EXTCLKREQ */

#define OMAP4_POLARITY_SHIFT			0

#define OMAP4_POLARITY_MASK			(1 << 0)



/* AUXCLKREQ0 */

#define OMAP4_MAPPING_SHIFT			2

#define OMAP4_MAPPING_MASK			(0x7 << 2)

#define OMAP4_MAPPING_WIDTH			3

#define OMAP4_ACCURACY_SHIFT			1

#define OMAP4_ACCURACY_MASK			(1 << 1)



/* AUXCLK0 */

#define OMAP4_CLKDIV_SHIFT			16

#define OMAP4_CLKDIV_MASK			(0xf << 16)

#define OMAP4_CLKDIV_WIDTH			4

#define OMAP4_DISABLECLK_SHIFT			9

#define OMAP4_DISABLECLK_MASK			(1 << 9)

#define OMAP4_ENABLE_SHIFT			8

#define OMAP4_ENABLE_MASK			(1 << 8)

#define OMAP4_SRCSELECT_SHIFT			1

#define OMAP4_SRCSELECT_MASK			(0x3 << 1)



/* RSTTIME */

#define OMAP4_RSTTIME_SHIFT			0

#define OMAP4_RSTTIME_MASK			(0xf << 0)



/* MODEMRSTCTRL */

#define OMAP4_WARMRST_SHIFT			1

#define OMAP4_WARMRST_MASK			(1 << 1)

#define OMAP4_COLDRST_SHIFT			0

#define OMAP4_COLDRST_MASK			(1 << 0)



/* EXTPWRONRSTCTRL */

#define OMAP4_PWRONRST_SHIFT			1

#define OMAP4_PWRONRST_MASK			(1 << 1)

#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT	0

#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK	(1 << 0)



/* EXTWARMRSTST */

#define OMAP4_EXTWARMRSTST_SHIFT		0

#define OMAP4_EXTWARMRSTST_MASK			(1 << 0)



/* APEWARMRSTST */

#define OMAP4_APEWARMRSTST_SHIFT		1

#define OMAP4_APEWARMRSTST_MASK			(1 << 1)



/* MODEMWARMRSTST */

#define OMAP4_MODEMWARMRSTST_SHIFT		2

#define OMAP4_MODEMWARMRSTST_MASK		(1 << 2)



/* D2DWARMRSTST */

#define OMAP4_D2DWARMRSTST_SHIFT		3

#define OMAP4_D2DWARMRSTST_MASK			(1 << 3)



#endif