Commit d915611e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-qcom', 'clk-versatile', 'clk-renesas', 'clk-sifive' and 'clk-ti' into clk-next 

 - duty cycle setting support on qcom clks
 - qcom MDM9607 GCC
 - qcom sc8180x display clks
 - qcom SM6125 GCC
 - Add TI am33xx spread spectrum clock support

* clk-qcom: (22 commits)
  clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepare
  clk: qcom: Add camera clock controller driver for SM8250
  dt-bindings: clock: add QCOM SM8250 camera clock bindings
  clk: qcom: clk-alpha-pll: add support for zonda pll
  clk/qcom: Remove unused variables
  clk: qcom: smd-rpmcc: Add support for MSM8226 rpm clocks
  clk: qcom: gcc: Add support for Global Clock controller found on MSM8226
  dt-bindings: clock: qcom: Add MSM8226 GCC clock bindings
  clk: qcom: Add SM6125 (TRINKET) GCC driver
  dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driver
  clk: qcom: gcc: Add support for a new frequency for SC7280
  clk: qcom: smd-rpm: Fix wrongly assigned RPM_SMD_PNOC_CLK
  dt-bindings: clock: qcom: rpmcc: Document MSM8226 compatible
  clk: qcom: dispcc-sm8250: Add EDP clocks
  clk: qcom: dispcc-sm8250: Add sc8180x support
  clk: qcom: smd-rpm: De-duplicate identical entries
  clk: qcom: smd-rpm: Switch to parent_data
  clk: qcom: Add MDM9607 GCC driver
  dt-bindings: clock: Add MDM9607 GCC clock bindings
  clk: qcom: cleanup some dev_err_probe() calls
  ...

* clk-versatile:
  clk: versatile: Depend on HAS_IOMEM
  clk: versatile: remove dependency on ARCH_*

* clk-renesas: (22 commits)
  clk: renesas: Add support for R9A07G044 SoC
  clk: renesas: Add CPG core wrapper for RZ/G2L SoC
  dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver
  dt-bindings: clock: Add r9a07g044 CPG Clock Definitions
  clk: renesas: r8a77995: Add ZA2 clock
  clk: renesas: cpg-mssr: Make srstclr[] comment block consistent
  clk: renesas: cpg-mssr: Remove unused [RM]MSTPCR() definitions
  clk: renesas: r9a06g032: Switch to .determine_rate()
  clk: renesas: div6: Implement range checking
  clk: renesas: div6: Consider all parents for requested rate
  clk: renesas: div6: Switch to .determine_rate()
  clk: renesas: div6: Simplify src mask handling
  clk: renesas: div6: Use clamp() instead of clamp_t()
  clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()
  clk: renesas: r8a779a0: Add ISPCS clocks
  clk: renesas: rcar-gen3: Add boost support to Z clocks
  clk: renesas: rcar-gen3: Add custom clock for PLLs
  clk: renesas: rcar-gen3: Increase Z clock accuracy
  clk: renesas: rcar-gen3: Grammar s/dependent of/dependent on/
  clk: renesas: rcar-gen3: Remove superfluous masking in cpg_z_clk_set_rate()
  ...

* clk-sifive:
  clk: analogbits: fix doc warning in wrpll-cln28hpc.c
  clk: sifive: Fix kernel-doc

* clk-ti:
  drivers: ti: remove redundant error message in adpll.c
  clk: keystone: syscon-clk: Add support for AM64 specific epwm-tbclk
  dt-bindings: clock: ehrpwm: Add support for AM64 specific compatible
  clk: ti: add am33xx/am43xx spread spectrum clock support
  ARM: dts: am43xx-clocks: add spread spectrum support
  ARM: dts: am33xx-clocks: add spread spectrum support
  dt-bindings: ti: dpll: add spread spectrum support
  clk: ti: fix typo in routine description
parents 7f54bf26 51c8b497 7f8a37a4 06abc753 9ba98c08

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

0 → 100644
+83 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.



  They provide the following functionalities:

    - The CPG block generates various core clocks,

    - The Module Standby Mode block provides two functions:

        1. Module Standby, providing a Clock Domain to control the clock supply

           to individual SoC devices,

        2. Reset Control, to perform a software reset of individual SoC devices.



properties:

  compatible:

    const: renesas,r9a07g044-cpg  # RZ/G2{L,LC}



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  clock-names:

    description:

      Clock source to CPG can be either from external clock input (EXCLK) or

      crystal oscillator (XIN/XOUT).

    const: extal



  '#clock-cells':

    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/r9a07g044-cpg.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.

    const: 2



  '#power-domain-cells':

    description:

      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and

      can be power-managed through Module Standby should refer to the CPG device

      node in their "power-domains" property, as documented by the generic PM

      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.

    const: 0



  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the <dt-bindings/clock/r9a07g044-cpg.h>.

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'

  - '#reset-cells'



additionalProperties: false



examples:

  - |

    cpg: clock-controller@11010000 {

            compatible = "renesas,r9a07g044-cpg";

            reg = <0x11010000 0x10000>;

            clocks = <&extal_clk>;

            clock-names = "extal";

            #clock-cells = <2>;

            #power-domain-cells = <0>;

            #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml

+3 −1
Original line number Diff line number Diff line
@@ -12,7 +12,9 @@ maintainers: 
properties:

  compatible:

    items:

      - const: ti,am654-ehrpwm-tbclk

      - enum:

          - ti,am654-ehrpwm-tbclk

          - ti,am64-epwm-tbclk

      - const: syscon



  "#clock-cells":

Documentation/devicetree/bindings/clock/ti/dpll.txt

+20 −0
Original line number Diff line number Diff line
@@ -42,6 +42,11 @@ Required properties: 
	"idlest" - contains the idle status register base address

	"mult-div1" - contains the multiplier / divider register base address

	"autoidle" - contains the autoidle register base address (optional)

	"ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains

		       the frequency spreading register base address (optional)

	"ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains

		        the modulation frequency register base address

			(optional)

  ti,am3-* dpll types do not have autoidle register

  ti,omap2-* dpll type does not support idlest / autoidle registers
@@ -51,6 +56,14 @@ Optional properties: 
	- ti,low-power-stop : DPLL supports low power stop mode, gating output

	- ti,low-power-bypass : DPLL output matches rate of parent bypass clock

	- ti,lock : DPLL locks in programmed rate

	- ti,min-div : the minimum divisor to start from to round the DPLL

		       target rate

	- ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency

			  spreading in permille (10th of a percent)

	- ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread

			      spectrum modulation frequency

	- ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean

			      to enable the downspread feature



Examples:

	dpll_core_ck: dpll_core_ck@44e00490 {
@@ -83,3 +96,10 @@ Examples: 
		clocks = <&sys_ck>, <&sys_ck>;

		reg = <0x0500>, <0x0540>;

	};



	dpll_disp_ck: dpll_disp_ck {

		#clock-cells = <0>;

		compatible = "ti,am3-dpll-no-gate-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;

	};

arch/arm/boot/dts/am33xx-clocks.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -164,7 +164,7 @@ dpll_core_ck: dpll_core_ck@490 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-core-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x0490>, <0x045c>, <0x0468>;

		reg = <0x0490>, <0x045c>, <0x0468>, <0x0460>, <0x0464>;

	};



	dpll_core_x2_ck: dpll_core_x2_ck {
@@ -204,7 +204,7 @@ dpll_mpu_ck: dpll_mpu_ck@488 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x0488>, <0x0420>, <0x042c>;

		reg = <0x0488>, <0x0420>, <0x042c>, <0x0424>, <0x0428>;

	};



	dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
@@ -220,7 +220,7 @@ dpll_ddr_ck: dpll_ddr_ck@494 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-no-gate-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x0494>, <0x0434>, <0x0440>;

		reg = <0x0494>, <0x0434>, <0x0440>, <0x0438>, <0x043c>;

	};



	dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
@@ -244,7 +244,7 @@ dpll_disp_ck: dpll_disp_ck@498 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-no-gate-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x0498>, <0x0448>, <0x0454>;

		reg = <0x0498>, <0x0448>, <0x0454>, <0x044c>, <0x0450>;

	};



	dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
@@ -261,7 +261,7 @@ dpll_per_ck: dpll_per_ck@48c { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-no-gate-j-type-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x048c>, <0x0470>, <0x049c>;

		reg = <0x048c>, <0x0470>, <0x049c>, <0x0474>, <0x0478>;

	};



	dpll_per_m2_ck: dpll_per_m2_ck@4ac {

arch/arm/boot/dts/am43xx-clocks.dtsi

+6 −6
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ dpll_core_ck: dpll_core_ck@2d20 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-core-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x2d20>, <0x2d24>, <0x2d2c>;

		reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;

	};



	dpll_core_x2_ck: dpll_core_x2_ck {
@@ -250,7 +250,7 @@ dpll_mpu_ck: dpll_mpu_ck@2d60 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x2d60>, <0x2d64>, <0x2d6c>;

		reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;

	};



	dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
@@ -276,7 +276,7 @@ dpll_ddr_ck: dpll_ddr_ck@2da0 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x2da0>, <0x2da4>, <0x2dac>;

		reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;

	};



	dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
@@ -294,7 +294,7 @@ dpll_disp_ck: dpll_disp_ck@2e20 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x2e20>, <0x2e24>, <0x2e2c>;

		reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;

	};



	dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
@@ -313,7 +313,7 @@ dpll_per_ck: dpll_per_ck@2de0 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-j-type-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x2de0>, <0x2de4>, <0x2dec>;

		reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;

	};



	dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
@@ -557,7 +557,7 @@ dpll_extdev_ck: dpll_extdev_ck@2e60 { 
		#clock-cells = <0>;

		compatible = "ti,am3-dpll-clock";

		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;

		reg = <0x2e60>, <0x2e64>, <0x2e6c>;

		reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;

	};



	dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {