Commit d9ab57ee authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Bjorn Andersson
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arm64: dts: qcom: sm6375: Supply clock from cpufreq node to CPUs 



Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. But this relationship is not represented in DTS so far.

So let's make cpufreq node as the clock provider and CPU nodes as the
consumers. The clock index for each CPU node is based on the frequency
domain index.

Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230215070400.5901-12-manivannan.sadhasivam@linaro.org
parent 2051f735

arch/arm64/boot/dts/qcom/sm6375.dtsi

+9 −0
Original line number Diff line number Diff line
@@ -40,6 +40,7 @@ CPU0: cpu@0 { 
			device_type = "cpu";

			compatible = "qcom,kryo660";

			reg = <0x0 0x0>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -59,6 +60,7 @@ CPU1: cpu@100 { 
			device_type = "cpu";

			compatible = "qcom,kryo660";

			reg = <0x0 0x100>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			next-level-cache = <&L2_100>;

			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -75,6 +77,7 @@ CPU2: cpu@200 { 
			device_type = "cpu";

			compatible = "qcom,kryo660";

			reg = <0x0 0x200>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			next-level-cache = <&L2_200>;

			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -91,6 +94,7 @@ CPU3: cpu@300 { 
			device_type = "cpu";

			compatible = "qcom,kryo660";

			reg = <0x0 0x300>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			next-level-cache = <&L2_300>;

			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -107,6 +111,7 @@ CPU4: cpu@400 { 
			device_type = "cpu";

			compatible = "qcom,kryo660";

			reg = <0x0 0x400>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			next-level-cache = <&L2_400>;

			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -123,6 +128,7 @@ CPU5: cpu@500 { 
			device_type = "cpu";

			compatible = "qcom,kryo660";

			reg = <0x0 0x500>;

			clocks = <&cpufreq_hw 0>;

			enable-method = "psci";

			next-level-cache = <&L2_500>;

			qcom,freq-domain = <&cpufreq_hw 0>;
@@ -140,6 +146,7 @@ CPU6: cpu@600 { 
			device_type = "cpu";

			compatible = "qcom,kryo660";

			reg = <0x0 0x600>;

			clocks = <&cpufreq_hw 1>;

			enable-method = "psci";

			next-level-cache = <&L2_600>;

			qcom,freq-domain = <&cpufreq_hw 1>;
@@ -156,6 +163,7 @@ CPU7: cpu@700 { 
			device_type = "cpu";

			compatible = "qcom,kryo660";

			reg = <0x0 0x700>;

			clocks = <&cpufreq_hw 1>;

			enable-method = "psci";

			next-level-cache = <&L2_700>;

			qcom,freq-domain = <&cpufreq_hw 1>;
@@ -1393,6 +1401,7 @@ cpufreq_hw: cpufreq@fd91000 { 
				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1";

			#freq-domain-cells = <1>;

			#clock-cells = <1>;

		};

	};