Commit d9db0fd6 authored by Paolo Bonzini's avatar Paolo Bonzini
Browse files

KVM: SEV: Mask CPUID[0x8000001F].eax according to supported features 



Add a reverse-CPUID entry for the memory encryption word, 0x8000001F.EAX,
and use it to override the supported CPUID flags reported to userspace.
Masking the reported CPUID flags avoids over-reporting KVM support, e.g.
without the mask a SEV-SNP capable CPU may incorrectly advertise SNP
support to userspace.

Clear SEV/SEV-ES if their corresponding module parameters are disabled,
and clear the memory encryption leaf completely if SEV is not fully
supported in KVM.  Advertise SME_COHERENT in addition to SEV and SEV-ES,
as the guest can use SME_COHERENT to avoid CLFLUSH operations.

Explicitly omit SME and VM_PAGE_FLUSH from the reporting.  These features
are used by KVM, but are not exposed to the guest, e.g. guest access to
related MSRs will fault.

Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Co-developed-by: default avatarSean Christopherson <seanjc@google.com>
Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
Message-Id: <20210422021125.3417167-6-seanjc@google.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent e8126bda

arch/x86/kvm/cpuid.c

+7 −1
Original line number Diff line number Diff line
@@ -558,6 +558,10 @@ void kvm_set_cpu_caps(void) 
	 */

	kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);



	kvm_cpu_cap_mask(CPUID_8000_001F_EAX,

		0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |

		F(SME_COHERENT));



	kvm_cpu_cap_mask(CPUID_C000_0001_EDX,

		F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |

		F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
@@ -945,8 +949,10 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 
		break;

	/* Support memory encryption cpuid if host supports it */

	case 0x8000001F:

		if (!boot_cpu_has(X86_FEATURE_SEV))

		if (!kvm_cpu_cap_has(X86_FEATURE_SEV))

			entry->eax = entry->ebx = entry->ecx = entry->edx = 0;

		else

			cpuid_entry_override(entry, CPUID_8000_001F_EAX);

		break;

	/*Add support for Centaur's CPUID instruction*/

	case 0xC0000000:

arch/x86/kvm/reverse_cpuid.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ static const struct cpuid_reg reverse_cpuid[] = { 
	[CPUID_7_EDX]         = {         7, 0, CPUID_EDX},

	[CPUID_7_1_EAX]       = {         7, 1, CPUID_EAX},

	[CPUID_12_EAX]        = {0x00000012, 0, CPUID_EAX},

	[CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX},

};



/*

arch/x86/kvm/svm/sev.c

+8 −0
Original line number Diff line number Diff line
@@ -1807,6 +1807,14 @@ void sev_vm_destroy(struct kvm *kvm) 
	sev_asid_free(sev);

}



void __init sev_set_cpu_caps(void)

{

	if (!sev)

		kvm_cpu_cap_clear(X86_FEATURE_SEV);

	if (!sev_es)

		kvm_cpu_cap_clear(X86_FEATURE_SEV_ES);

}



void __init sev_hardware_setup(void)

{

	unsigned int eax, ebx, ecx, edx, sev_asid_count, sev_es_asid_count;

arch/x86/kvm/svm/svm.c

+3 −0
Original line number Diff line number Diff line
@@ -923,6 +923,9 @@ static __init void svm_set_cpu_caps(void) 
	if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||

	    boot_cpu_has(X86_FEATURE_AMD_SSBD))

		kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);



	/* CPUID 0x8000001F (SME/SEV features) */

	sev_set_cpu_caps();

}



static __init int svm_hardware_setup(void)

arch/x86/kvm/svm/svm.h

+1 −0
Original line number Diff line number Diff line
@@ -575,6 +575,7 @@ int svm_unregister_enc_region(struct kvm *kvm, 
			      struct kvm_enc_region *range);

int svm_vm_copy_asid_from(struct kvm *kvm, unsigned int source_fd);

void pre_sev_run(struct vcpu_svm *svm, int cpu);

void __init sev_set_cpu_caps(void);

void __init sev_hardware_setup(void);

void sev_hardware_teardown(void);

void sev_free_vcpu(struct kvm_vcpu *vcpu);