Commit dbf5256b authored by Joshua Aberback's avatar Joshua Aberback Committed by Alex Deucher
Browse files

drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2 



[Why]
Prior commit "Blank HUBP during pixel data blank for DCN30"
missed the call to set_disp_pattern_generator from
set_crtc_test_pattern, which re-exposed the issue for which
we initially blocked active-only p-state switching.

[How]
 - remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version
 - new hwss funciton set_disp_pattern_generator
 - dcn20 version just calls opp_set_disp_pattern_generator
 - dcn30 version implements the HUBP blank

Signed-off-by: default avatarJoshua Aberback <joshua.aberback@amd.com>
Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ec76bd6f

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+32 −30
Original line number Diff line number Diff line
@@ -3848,7 +3848,7 @@ static void set_crtc_test_pattern(struct dc_link *link, 
		if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

			pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

				controller_test_pattern, color_depth);

		else if (opp->funcs->opp_set_disp_pattern_generator) {

		else if (link->dc->hwss.set_disp_pattern_generator) {

			struct pipe_ctx *odm_pipe;

			enum controller_dp_color_space controller_color_space;

			int opp_cnt = 1;
@@ -3878,7 +3878,8 @@ static void set_crtc_test_pattern(struct dc_link *link, 
			dpg_width = width / opp_cnt;

			offset = dpg_width;



			opp->funcs->opp_set_disp_pattern_generator(opp,

			link->dc->hwss.set_disp_pattern_generator(link->dc,

					pipe_ctx,

					controller_test_pattern,

					controller_color_space,

					color_depth,
@@ -3889,8 +3890,10 @@ static void set_crtc_test_pattern(struct dc_link *link, 


			for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;



				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);

				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,

				link->dc->hwss.set_disp_pattern_generator(link->dc,

						odm_pipe,

						controller_test_pattern,

						controller_color_space,

						color_depth,
@@ -3913,7 +3916,7 @@ static void set_crtc_test_pattern(struct dc_link *link, 
			pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,

				color_depth);

		else if (opp->funcs->opp_set_disp_pattern_generator) {

		else if (link->dc->hwss.set_disp_pattern_generator) {

			struct pipe_ctx *odm_pipe;

			int opp_cnt = 1;

			int dpg_width = width;
@@ -3926,7 +3929,8 @@ static void set_crtc_test_pattern(struct dc_link *link, 
				struct output_pixel_processor *odm_opp = odm_pipe->stream_res.opp;



				odm_opp->funcs->opp_program_bit_depth_reduction(odm_opp, &params);

				odm_opp->funcs->opp_set_disp_pattern_generator(odm_opp,

				link->dc->hwss.set_disp_pattern_generator(link->dc,

						odm_pipe,

						CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,

						CONTROLLER_DP_COLOR_SPACE_UDEFINED,

						color_depth,
@@ -3935,7 +3939,8 @@ static void set_crtc_test_pattern(struct dc_link *link, 
						height,

						0);

			}

			opp->funcs->opp_set_disp_pattern_generator(opp,

			link->dc->hwss.set_disp_pattern_generator(link->dc,

					pipe_ctx,

					CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,

					CONTROLLER_DP_COLOR_SPACE_UDEFINED,

					color_depth,
@@ -3977,10 +3982,7 @@ bool dc_link_dp_set_test_pattern( 
		}

	}



	/* Reset CRTC Test Pattern if it is currently running and request

	 * is VideoMode Reset DP Phy Test Pattern if it is currently running

	 * and request is VideoMode

	 */

	/* Reset CRTC Test Pattern if it is currently running and request is VideoMode */

	if (link->test_pattern_enabled && test_pattern ==

			DP_TEST_PATTERN_VIDEO_MODE) {

		/* Set CRTC Test Pattern */

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+16 −4
Original line number Diff line number Diff line
@@ -1030,8 +1030,8 @@ void dcn20_blank_pixel_data( 
		test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;

	}



	stream_res->opp->funcs->opp_set_disp_pattern_generator(

			stream_res->opp,

	dc->hwss.set_disp_pattern_generator(dc,

			pipe_ctx,

			test_pattern,

			test_pattern_color_space,

			stream->timing.display_color_depth,
@@ -1041,8 +1041,8 @@ void dcn20_blank_pixel_data( 
			0);



	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {

		odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(

				odm_pipe->stream_res.opp,

		dc->hwss.set_disp_pattern_generator(dc,

				odm_pipe,

				dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?

						CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,

				test_pattern_color_space,
@@ -2569,3 +2569,15 @@ bool dcn20_optimize_timing_for_fsft(struct dc *dc, 
	return true;

}

#endif



void dcn20_set_disp_pattern_generator(const struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		enum controller_dp_test_pattern test_pattern,

		enum controller_dp_color_space color_space,

		enum dc_color_depth color_depth,

		const struct tg_color *solid_color,

		int width, int height, int offset)

{

	pipe_ctx->stream_res.opp->funcs->opp_set_disp_pattern_generator(pipe_ctx->stream_res.opp, test_pattern,

			color_space, color_depth, solid_color, width, height, offset);

}
 
 No newline at end of file

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h

+9 −0
Original line number Diff line number Diff line
@@ -137,5 +137,14 @@ bool dcn20_optimize_timing_for_fsft(struct dc *dc, 
		struct dc_crtc_timing *timing,

		unsigned int max_input_rate_in_khz);

#endif



void dcn20_set_disp_pattern_generator(const struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		enum controller_dp_test_pattern test_pattern,

		enum controller_dp_color_space color_space,

		enum dc_color_depth color_depth,

		const struct tg_color *solid_color,

		int width, int height, int offset);



#endif /* __DC_HWSS_DCN20_H__ */

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_init.c

+1 −0
Original line number Diff line number Diff line
@@ -93,6 +93,7 @@ static const struct hw_sequencer_funcs dcn20_funcs = { 
#ifndef TRIM_FSFT

	.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,

#endif

	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,

};



static const struct hwseq_private_funcs dcn20_private_funcs = {

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c

+1 −0
Original line number Diff line number Diff line
@@ -98,6 +98,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = { 
	.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,

#endif

	.is_abm_supported = dcn21_is_abm_supported,

	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,

};



static const struct hwseq_private_funcs dcn21_private_funcs = {