Commit dc3499c7 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: accommodate DOMAIN/PL_DOORBELL 



This patch adds changes:
- to accommodate the new GEM domain for DOORBELLs
- to accommodate the new TTM PL for DOORBELLs

in order to manage doorbell pages as GEM object.

V2: Addressed reviwe comments from Christian
    - drop the doorbell changes for pinning/unpinning
    - drop the doorbell changes for dma-buf map
    - drop the doorbell changes for sgt
    - no need to handle TTM_PL_FLAG_CONTIGUOUS for doorbell
    - add caching type for doorbell

V3: - Removed unrelated empty line (Christian)
    - Add PL_DOORBELL in mem_type_to_domain() as well (Alex)

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: default avatarChristian Koenig <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarShashank Sharma <shashank.sharma@amd.com>
parent 05c899ea

drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

+10 −1
Original line number Diff line number Diff line
@@ -158,6 +158,14 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) 
		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) {

		places[c].fpfn = 0;

		places[c].lpfn = 0;

		places[c].mem_type = AMDGPU_PL_DOORBELL;

		places[c].flags = 0;

		c++;

	}



	if (domain & AMDGPU_GEM_DOMAIN_GTT) {

		places[c].fpfn = 0;

		places[c].lpfn = 0;
@@ -477,7 +485,7 @@ static bool amdgpu_bo_validate_size(struct amdgpu_device *adev, 
		goto fail;

	}



	/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */

	/* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */

	return true;



fail:
@@ -1029,6 +1037,7 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo) 
	} else if (bo->tbo.resource->mem_type == TTM_PL_TT) {

		atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);

	}



}



static const char * const amdgpu_vram_names[] = {

drivers/gpu/drm/amd/amdgpu/amdgpu_object.h

+2 −0
Original line number Diff line number Diff line
@@ -182,6 +182,8 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 
		return AMDGPU_GEM_DOMAIN_GWS;

	case AMDGPU_PL_OA:

		return AMDGPU_GEM_DOMAIN_OA;

	case AMDGPU_PL_DOORBELL:

		return AMDGPU_GEM_DOMAIN_DOORBELL;

	default:

		break;

	}

drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h

+2 −0
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ static inline void amdgpu_res_first(struct ttm_resource *res, 
		cur->node = block;

		break;

	case TTM_PL_TT:

	case AMDGPU_PL_DOORBELL:

		node = to_ttm_range_mgr_node(res)->mm_nodes;

		while (start >= node->size << PAGE_SHIFT)

			start -= node++->size << PAGE_SHIFT;
@@ -152,6 +153,7 @@ static inline void amdgpu_res_next(struct amdgpu_res_cursor *cur, uint64_t size) 
		cur->size = min(amdgpu_vram_mgr_block_size(block), cur->remaining);

		break;

	case TTM_PL_TT:

	case AMDGPU_PL_DOORBELL:

		node = cur->node;



		cur->node = ++node;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

+15 −1
Original line number Diff line number Diff line
@@ -127,6 +127,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, 
	case AMDGPU_PL_GDS:

	case AMDGPU_PL_GWS:

	case AMDGPU_PL_OA:

	case AMDGPU_PL_DOORBELL:

		placement->num_placement = 0;

		placement->num_busy_placement = 0;

		return;
@@ -496,9 +497,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, 
	if (old_mem->mem_type == AMDGPU_PL_GDS ||

	    old_mem->mem_type == AMDGPU_PL_GWS ||

	    old_mem->mem_type == AMDGPU_PL_OA ||

	    old_mem->mem_type == AMDGPU_PL_DOORBELL ||

	    new_mem->mem_type == AMDGPU_PL_GDS ||

	    new_mem->mem_type == AMDGPU_PL_GWS ||

	    new_mem->mem_type == AMDGPU_PL_OA) {

	    new_mem->mem_type == AMDGPU_PL_OA ||

	    new_mem->mem_type == AMDGPU_PL_DOORBELL) {

		/* Nothing to save here */

		ttm_bo_move_null(bo, new_mem);

		goto out;
@@ -582,6 +585,12 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, 
		mem->bus.offset += adev->gmc.aper_base;

		mem->bus.is_iomem = true;

		break;

	case AMDGPU_PL_DOORBELL:

		mem->bus.offset = mem->start << PAGE_SHIFT;

		mem->bus.offset += adev->doorbell.base;

		mem->bus.is_iomem = true;

		mem->bus.caching = ttm_uncached;

		break;

	default:

		return -EINVAL;

	}
@@ -596,6 +605,10 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, 


	amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0,

			 &cursor);



	if (bo->resource->mem_type == AMDGPU_PL_DOORBELL)

		return ((uint64_t)(adev->doorbell.base + cursor.start)) >> PAGE_SHIFT;



	return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;

}
@@ -1305,6 +1318,7 @@ uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem) 
		flags |= AMDGPU_PTE_VALID;



	if (mem && (mem->mem_type == TTM_PL_TT ||

		    mem->mem_type == AMDGPU_PL_DOORBELL ||

		    mem->mem_type == AMDGPU_PL_PREEMPT)) {

		flags |= AMDGPU_PTE_SYSTEM;

drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#define AMDGPU_PL_GWS		(TTM_PL_PRIV + 1)

#define AMDGPU_PL_OA		(TTM_PL_PRIV + 2)

#define AMDGPU_PL_PREEMPT	(TTM_PL_PRIV + 3)

#define AMDGPU_PL_DOORBELL	(TTM_PL_PRIV + 4)



#define AMDGPU_GTT_MAX_TRANSFER_SIZE	512

#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS	2