Commit dcb3f7c9 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: drop smart_dma_rev from dpu_caps 



The code doesn't use dpu_caps::smart_dma_rev field. It checks if the
corresponding feature is enabled in the SSPP features. Drop the
smart_dma_rev field completely.

Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/527369/
Link: https://lore.kernel.org/r/20230316161653.4106395-31-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 8b409996

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c

+0 −13
Original line number Diff line number Diff line
@@ -323,7 +323,6 @@ static const struct dpu_caps msm8998_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0x7,

	.qseed_type = DPU_SSPP_SCALER_QSEED3,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V1,

	.ubwc_version = DPU_HW_UBWC_VER_10,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -338,7 +337,6 @@ static const struct dpu_caps msm8998_dpu_caps = { 
static const struct dpu_caps qcm2290_dpu_caps = {

	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,

	.max_mixer_blendstages = 0x4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,

	.has_dim_layer = true,

	.has_idle_pc = true,

	.max_linewidth = 2160,
@@ -349,7 +347,6 @@ static const struct dpu_caps sdm845_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED3,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,

	.ubwc_version = DPU_HW_UBWC_VER_20,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -365,7 +362,6 @@ static const struct dpu_caps sc7180_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0x9,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,

	.ubwc_version = DPU_HW_UBWC_VER_20,

	.has_dim_layer = true,

	.has_idle_pc = true,
@@ -377,7 +373,6 @@ static const struct dpu_caps sm6115_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,

	.max_mixer_blendstages = 0x4,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_10,

	.has_dim_layer = true,

	.has_idle_pc = true,
@@ -389,7 +384,6 @@ static const struct dpu_caps sm8150_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED3,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_30,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -405,7 +399,6 @@ static const struct dpu_caps sc8180x_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED3,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_30,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -421,7 +414,6 @@ static const struct dpu_caps sc8280xp_dpu_caps = { 
	.max_mixer_width = 2560,

	.max_mixer_blendstages = 11,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_40,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -435,7 +427,6 @@ static const struct dpu_caps sm8250_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_40,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -449,7 +440,6 @@ static const struct dpu_caps sm8350_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_40,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -463,7 +453,6 @@ static const struct dpu_caps sm8450_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_40,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -477,7 +466,6 @@ static const struct dpu_caps sm8550_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0xb,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */

	.ubwc_version = DPU_HW_UBWC_VER_40,

	.has_src_split = true,

	.has_dim_layer = true,
@@ -491,7 +479,6 @@ static const struct dpu_caps sc7280_dpu_caps = { 
	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,

	.max_mixer_blendstages = 0x7,

	.qseed_type = DPU_SSPP_SCALER_QSEED4,

	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,

	.ubwc_version = DPU_HW_UBWC_VER_30,

	.has_dim_layer = true,

	.has_idle_pc = true,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

+0 −2
Original line number Diff line number Diff line
@@ -399,7 +399,6 @@ struct dpu_rotation_cfg { 
 * @max_mixer_blendstages max layer mixer blend stages or

 *                       supported z order

 * @qseed_type         qseed2 or qseed3 support.

 * @smart_dma_rev      Supported version of SmartDMA feature.

 * @ubwc_version       UBWC feature version (0x0 for not supported)

 * @has_src_split      source split feature status

 * @has_dim_layer      dim layer feature status
@@ -414,7 +413,6 @@ struct dpu_caps { 
	u32 max_mixer_width;

	u32 max_mixer_blendstages;

	u32 qseed_type;

	u32 smart_dma_rev;

	u32 ubwc_version;

	bool has_src_split;

	bool has_dim_layer;