Commit dccdbf3f authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher
Browse files

drm/amdgpu: initialize IP offset for sienna_cichlid (v2) 



Add IP offset headers and state.

V2: squash in updates (Alex)

Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 117910ed

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce 
amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \

	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o

	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o



# add DF block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/nv.c

+3 −0
Original line number Diff line number Diff line
@@ -407,6 +407,9 @@ static int nv_reg_base_init(struct amdgpu_device *adev) 
	case CHIP_NAVI12:

		navi12_reg_base_init(adev);

		break;

	case CHIP_SIENNA_CICHLID:

		sienna_cichlid_reg_base_init(adev);

		break;

	default:

		return -EINVAL;

	}

drivers/gpu/drm/amd/amdgpu/nv.h

+1 −0
Original line number Diff line number Diff line
@@ -32,4 +32,5 @@ int nv_set_ip_blocks(struct amdgpu_device *adev); 
int navi10_reg_base_init(struct amdgpu_device *adev);

int navi14_reg_base_init(struct amdgpu_device *adev);

int navi12_reg_base_init(struct amdgpu_device *adev);

int sienna_cichlid_reg_base_init(struct amdgpu_device *adev);

#endif

drivers/gpu/drm/amd/amdgpu/sienna_cichlid_reg_init.c

0 → 100644
+54 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2019 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include "amdgpu.h"

#include "nv.h"



#include "soc15_common.h"

#include "soc15_hw_ip.h"

#include "sienna_cichlid_ip_offset.h"



int sienna_cichlid_reg_base_init(struct amdgpu_device *adev)

{

	/* HW has more IP blocks,  only initialized the blocke needed by driver */

	uint32_t i;

	for (i = 0 ; i < MAX_INSTANCE ; ++i) {

		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));

		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

		adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));

		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

		adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

		adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

	}

	return 0;

}

drivers/gpu/drm/amd/include/sienna_cichlid_ip_offset.h

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File added.

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