Commit dd67d7a6 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/pm: mark pcie link/speed arrays as const



They are read only.

Noticed-by: default avatarDave Airlie <airlied@linux.ie>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 266b2d25
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+2 −2
Original line number Original line Diff line number Diff line
@@ -61,8 +61,8 @@
#define LINK_WIDTH_MAX			6
#define LINK_WIDTH_MAX			6
#define LINK_SPEED_MAX			3
#define LINK_SPEED_MAX			3


static __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
static const __maybe_unused uint16_t link_width[] = {0, 1, 2, 4, 8, 12, 16};
static __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160};
static const __maybe_unused uint16_t link_speed[] = {25, 50, 80, 160};


static const
static const
struct smu_temperature_range __maybe_unused smu11_thermal_policy[] =
struct smu_temperature_range __maybe_unused smu11_thermal_policy[] =
+2 −2
Original line number Original line Diff line number Diff line
@@ -52,8 +52,8 @@


#define LINK_WIDTH_MAX				6
#define LINK_WIDTH_MAX				6
#define LINK_SPEED_MAX				3
#define LINK_SPEED_MAX				3
static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static int link_speed[] = {25, 50, 80, 160};
static const int link_speed[] = {25, 50, 80, 160};


static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
		enum pp_clock_type type, uint32_t mask);
		enum pp_clock_type type, uint32_t mask);
+2 −2
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@@ -57,8 +57,8 @@


#define LINK_WIDTH_MAX				6
#define LINK_WIDTH_MAX				6
#define LINK_SPEED_MAX				3
#define LINK_SPEED_MAX				3
static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static int link_speed[] = {25, 50, 80, 160};
static const int link_speed[] = {25, 50, 80, 160};


static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
{
{
+2 −2
Original line number Original line Diff line number Diff line
@@ -72,8 +72,8 @@ MODULE_FIRMWARE("amdgpu/aldebaran_smc.bin");
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
#define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE


static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
static int link_speed[] = {25, 50, 80, 160};
static const int link_speed[] = {25, 50, 80, 160};


int smu_v13_0_init_microcode(struct smu_context *smu)
int smu_v13_0_init_microcode(struct smu_context *smu)
{
{