Loading arch/arm/mach-ixp4xx/include/mach/cpu.h +20 −15 Original line number Diff line number Diff line Loading @@ -17,26 +17,31 @@ #include <asm/cputype.h> /* Processor id value in CP15 Register 0 */ #define IXP425_PROCESSOR_ID_VALUE 0x690541c0 #define IXP435_PROCESSOR_ID_VALUE 0x69054040 #define IXP465_PROCESSOR_ID_VALUE 0x69054200 #define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0 #define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ IXP425_PROCESSOR_ID_VALUE) #define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ IXP435_PROCESSOR_ID_VALUE) #define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ IXP465_PROCESSOR_ID_VALUE) #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */ #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0 #define IXP43X_PROCESSOR_ID_VALUE 0x69054040 #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0 #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ IXP42X_PROCESSOR_ID_VALUE) #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ IXP43X_PROCESSOR_ID_VALUE) #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \ IXP46X_PROCESSOR_ID_VALUE) static inline u32 ixp4xx_read_feature_bits(void) { unsigned int val = ~*IXP4XX_EXP_CFG2; val &= ~IXP4XX_FEATURE_RESERVED; if (!cpu_is_ixp46x()) val &= ~IXP4XX_FEATURE_IXP46X_ONLY; return val; if (cpu_is_ixp42x()) return val & IXP42X_FEATURE_MASK; if (cpu_is_ixp43x()) return val & IXP43X_FEATURE_MASK; return val & IXP46X_FEATURE_MASK; } static inline void ixp4xx_write_feature_bits(u32 value) Loading arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +32 −10 Original line number Diff line number Diff line Loading @@ -604,6 +604,7 @@ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ /* "fuse" bits of IXP_EXP_CFG2 */ /* All IXP4xx CPUs */ #define IXP4XX_FEATURE_RCOMP (1 << 0) #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) #define IXP4XX_FEATURE_HASH (1 << 2) Loading @@ -619,20 +620,41 @@ #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) #define IXP4XX_FEATURE_PCI (1 << 14) #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ IXP4XX_FEATURE_USB_DEVICE | \ IXP4XX_FEATURE_HASH | \ IXP4XX_FEATURE_AES | \ IXP4XX_FEATURE_DES | \ IXP4XX_FEATURE_HDLC | \ IXP4XX_FEATURE_AAL | \ IXP4XX_FEATURE_HSS | \ IXP4XX_FEATURE_UTOPIA | \ IXP4XX_FEATURE_NPEB_ETH0 | \ IXP4XX_FEATURE_NPEC_ETH | \ IXP4XX_FEATURE_RESET_NPEA | \ IXP4XX_FEATURE_RESET_NPEB | \ IXP4XX_FEATURE_RESET_NPEC | \ IXP4XX_FEATURE_PCI | \ IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ IXP4XX_FEATURE_XSCALE_MAX_FREQ) /* IXP43x/46x CPUs */ #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) #define IXP4XX_FEATURE_USB_HOST (1 << 18) #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ IXP4XX_FEATURE_ECC_TIMESYNC | \ IXP4XX_FEATURE_USB_HOST | \ IXP4XX_FEATURE_NPEA_ETH) /* IXP46x CPU (including IXP455) only */ #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) #define IXP4XX_FEATURE_RSA (1 << 21) #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) #define IXP4XX_FEATURE_RESERVED (0xFF << 24) #define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ IXP4XX_FEATURE_USB_HOST | \ IXP4XX_FEATURE_NPEA_ETH | \ #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ IXP4XX_FEATURE_RSA | \ IXP4XX_FEATURE_XSCALE_MAX_FREQ) IXP4XX_FEATURE_RSA) #endif Loading
arch/arm/mach-ixp4xx/include/mach/cpu.h +20 −15 Original line number Diff line number Diff line Loading @@ -17,26 +17,31 @@ #include <asm/cputype.h> /* Processor id value in CP15 Register 0 */ #define IXP425_PROCESSOR_ID_VALUE 0x690541c0 #define IXP435_PROCESSOR_ID_VALUE 0x69054040 #define IXP465_PROCESSOR_ID_VALUE 0x69054200 #define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0 #define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ IXP425_PROCESSOR_ID_VALUE) #define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ IXP435_PROCESSOR_ID_VALUE) #define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ IXP465_PROCESSOR_ID_VALUE) #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */ #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0 #define IXP43X_PROCESSOR_ID_VALUE 0x69054040 #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0 #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ IXP42X_PROCESSOR_ID_VALUE) #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ IXP43X_PROCESSOR_ID_VALUE) #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \ IXP46X_PROCESSOR_ID_VALUE) static inline u32 ixp4xx_read_feature_bits(void) { unsigned int val = ~*IXP4XX_EXP_CFG2; val &= ~IXP4XX_FEATURE_RESERVED; if (!cpu_is_ixp46x()) val &= ~IXP4XX_FEATURE_IXP46X_ONLY; return val; if (cpu_is_ixp42x()) return val & IXP42X_FEATURE_MASK; if (cpu_is_ixp43x()) return val & IXP43X_FEATURE_MASK; return val & IXP46X_FEATURE_MASK; } static inline void ixp4xx_write_feature_bits(u32 value) Loading
arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +32 −10 Original line number Diff line number Diff line Loading @@ -604,6 +604,7 @@ #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ /* "fuse" bits of IXP_EXP_CFG2 */ /* All IXP4xx CPUs */ #define IXP4XX_FEATURE_RCOMP (1 << 0) #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) #define IXP4XX_FEATURE_HASH (1 << 2) Loading @@ -619,20 +620,41 @@ #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) #define IXP4XX_FEATURE_PCI (1 << 14) #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ IXP4XX_FEATURE_USB_DEVICE | \ IXP4XX_FEATURE_HASH | \ IXP4XX_FEATURE_AES | \ IXP4XX_FEATURE_DES | \ IXP4XX_FEATURE_HDLC | \ IXP4XX_FEATURE_AAL | \ IXP4XX_FEATURE_HSS | \ IXP4XX_FEATURE_UTOPIA | \ IXP4XX_FEATURE_NPEB_ETH0 | \ IXP4XX_FEATURE_NPEC_ETH | \ IXP4XX_FEATURE_RESET_NPEA | \ IXP4XX_FEATURE_RESET_NPEB | \ IXP4XX_FEATURE_RESET_NPEC | \ IXP4XX_FEATURE_PCI | \ IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ IXP4XX_FEATURE_XSCALE_MAX_FREQ) /* IXP43x/46x CPUs */ #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) #define IXP4XX_FEATURE_USB_HOST (1 << 18) #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ IXP4XX_FEATURE_ECC_TIMESYNC | \ IXP4XX_FEATURE_USB_HOST | \ IXP4XX_FEATURE_NPEA_ETH) /* IXP46x CPU (including IXP455) only */ #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) #define IXP4XX_FEATURE_RSA (1 << 21) #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) #define IXP4XX_FEATURE_RESERVED (0xFF << 24) #define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ IXP4XX_FEATURE_USB_HOST | \ IXP4XX_FEATURE_NPEA_ETH | \ #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ IXP4XX_FEATURE_RSA | \ IXP4XX_FEATURE_XSCALE_MAX_FREQ) IXP4XX_FEATURE_RSA) #endif