Commit de930140 authored by Alvin Lee's avatar Alvin Lee Committed by Alex Deucher
Browse files

drm/amd/display: Update to correct min FCLK when construction BB 



[Description]
- For min FCLK, choose the min of 300Mhz and PMFW requirement
- Also only apply min DET check in DML for non-UR cases

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarQingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: default avatarAlvin Lee <Alvin.Lee2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4652ae7a

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+3 −2
Original line number Diff line number Diff line
@@ -2315,6 +2315,9 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
			num_dcfclk_dpms++;

	}



	if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)

		min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;



	if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)

		return -1;
@@ -2423,7 +2426,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
		for (i = *num_entries - 1; i >= 0 ; i--) {

			if (table[i].fabricclk_mhz < min_fclk_mhz) {

				table[i].fabricclk_mhz = min_fclk_mhz;

				break;

			}

		}

	}
@@ -2432,7 +2434,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
	for (i = *num_entries - 1; i >= 0 ; i--) {

		if (table[i].dcfclk_mhz < min_dcfclk_mhz) {

			table[i].dcfclk_mhz = min_dcfclk_mhz;

			break;

		}

	}

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

+4 −2
Original line number Diff line number Diff line
@@ -689,7 +689,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman 
						mode_lib->vba.PixelClock,

						mode_lib->vba.VRatio,

						mode_lib->vba.VRatioChroma,

						mode_lib->vba.UsesMALLForPStateChange);

						mode_lib->vba.UsesMALLForPStateChange,

						mode_lib->vba.UseUnboundedRequesting);



	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {

		v->MaxVStartupLines[k] = ((mode_lib->vba.Interlace[k] &&
@@ -3215,7 +3216,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
					mode_lib->vba.PixelClock,

					mode_lib->vba.VRatio,

					mode_lib->vba.VRatioChroma,

					mode_lib->vba.UsesMALLForPStateChange);

					mode_lib->vba.UsesMALLForPStateChange,

					mode_lib->vba.UseUnboundedRequesting);



			v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.VMDataOnlyReturnBWPerState = dml32_get_return_bw_mbps_vm_only(&mode_lib->vba.soc, i,

					mode_lib->vba.DCFCLKState[i][j], mode_lib->vba.FabricClockPerState[i],

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

+5 −1
Original line number Diff line number Diff line
@@ -6271,7 +6271,8 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface 
		double	PixelClock[],

		double	VRatioY[],

		double	VRatioC[],

		enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[])

		enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[],

		enum unbounded_requesting_policy UseUnboundedRequesting)

{

	int k;

	double SwathSizeAllSurfaces = 0;
@@ -6283,6 +6284,9 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface 
	double SwathSizePerSurfaceC[DC__NUM_DPP__MAX];

	bool NotEnoughDETSwathFillLatencyHiding = false;



	if (UseUnboundedRequesting == dm_unbounded_requesting)

		return false;



	/* calculate sum of single swath size for all pipes in bytes */

	for (k = 0; k < NumberOfActiveSurfaces; k++) {

		SwathSizePerSurfaceY[k] = SwathHeightY[k] * SwathWidthY[k] * BytePerPixelInDETY[k] * NumOfDPP[k];

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h

+2 −1
Original line number Diff line number Diff line
@@ -1163,6 +1163,7 @@ bool dml32_CalculateDETSwathFillLatencyHiding(unsigned int NumberOfActiveSurface 
		double	PixelClock[],

		double	VRatioY[],

		double	VRatioC[],

		enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[]);

		enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[],

		enum unbounded_requesting_policy UseUnboundedRequesting);



#endif

drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c

+3 −2
Original line number Diff line number Diff line
@@ -294,6 +294,9 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
			num_dcfclk_dpms++;

	}



	if (num_dcfclk_dpms > 0 && bw_params->clk_table.entries[0].fclk_mhz > min_fclk_mhz)

		min_fclk_mhz = bw_params->clk_table.entries[0].fclk_mhz;



	if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)

		return -1;
@@ -402,7 +405,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
		for (i = *num_entries - 1; i >= 0 ; i--) {

			if (table[i].fabricclk_mhz < min_fclk_mhz) {

				table[i].fabricclk_mhz = min_fclk_mhz;

				break;

			}

		}

	}
@@ -411,7 +413,6 @@ static int build_synthetic_soc_states(struct clk_bw_params *bw_params, 
	for (i = *num_entries - 1; i >= 0 ; i--) {

		if (table[i].dcfclk_mhz < min_dcfclk_mhz) {

			table[i].dcfclk_mhz = min_dcfclk_mhz;

			break;

		}

	}