Commit e0f6fa0d authored by Dan Williams's avatar Dan Williams
Browse files

Merge branch 'for-6.2/cxl-aer' into for-6.2/cxl 

Pick up CXL AER handling and correctable error extensions. Resolve
conflicts with cxl_pmem_wq reworks and RCH support.
parents 95dddcb5 6155ccc9

Documentation/PCI/pci-error-recovery.rst

+7 −0
Original line number Diff line number Diff line
@@ -83,6 +83,7 @@ This structure has the form:: 
		int (*mmio_enabled)(struct pci_dev *dev);

		int (*slot_reset)(struct pci_dev *dev);

		void (*resume)(struct pci_dev *dev);

		void (*cor_error_detected)(struct pci_dev *dev);

	};



The possible channel states are::
@@ -422,5 +423,11 @@ That is, the recovery API only requires that: 
   - drivers/net/cxgb3

   - drivers/net/s2io.c



   The cor_error_detected() callback is invoked in handle_error_source() when

   the error severity is "correctable". The callback is optional and allows

   additional logging to be done if desired. See example:



   - drivers/cxl/pci.c



The End

-------

drivers/cxl/core/hdm.c

+19 −14
Original line number Diff line number Diff line
@@ -82,18 +82,23 @@ static void parse_hdm_decoder_caps(struct cxl_hdm *cxlhdm) 
		cxlhdm->interleave_mask |= GENMASK(14, 12);

}



static void __iomem *map_hdm_decoder_regs(struct cxl_port *port,

					  void __iomem *crb)

static int map_hdm_decoder_regs(struct cxl_port *port, void __iomem *crb,

				struct cxl_component_regs *regs)

{

	struct cxl_component_reg_map map;

	struct cxl_register_map map = {

		.resource = port->component_reg_phys,

		.base = crb,

		.max_size = CXL_COMPONENT_REG_BLOCK_SIZE,

	};



	cxl_probe_component_regs(&port->dev, crb, &map);

	if (!map.hdm_decoder.valid) {

	cxl_probe_component_regs(&port->dev, crb, &map.component_map);

	if (!map.component_map.hdm_decoder.valid) {

		dev_err(&port->dev, "HDM decoder registers invalid\n");

		return IOMEM_ERR_PTR(-ENXIO);

		return -ENXIO;

	}



	return crb + map.hdm_decoder.offset;

	return cxl_map_component_regs(&port->dev, regs, &map,

				      BIT(CXL_CM_CAP_CAP_ID_HDM));

}



/**
@@ -103,25 +108,25 @@ static void __iomem *map_hdm_decoder_regs(struct cxl_port *port, 
struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port)

{

	struct device *dev = &port->dev;

	void __iomem *crb, *hdm;

	struct cxl_hdm *cxlhdm;

	void __iomem *crb;

	int rc;



	cxlhdm = devm_kzalloc(dev, sizeof(*cxlhdm), GFP_KERNEL);

	if (!cxlhdm)

		return ERR_PTR(-ENOMEM);



	cxlhdm->port = port;

	crb = devm_cxl_iomap_block(dev, port->component_reg_phys,

				   CXL_COMPONENT_REG_BLOCK_SIZE);

	crb = ioremap(port->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);

	if (!crb) {

		dev_err(dev, "No component registers mapped\n");

		return ERR_PTR(-ENXIO);

	}



	hdm = map_hdm_decoder_regs(port, crb);

	if (IS_ERR(hdm))

		return ERR_CAST(hdm);

	cxlhdm->regs.hdm_decoder = hdm;

	rc = map_hdm_decoder_regs(port, crb, &cxlhdm->regs);

	iounmap(crb);

	if (rc)

		return ERR_PTR(rc);



	parse_hdm_decoder_caps(cxlhdm);

	if (cxlhdm->decoder_count == 0) {

drivers/cxl/core/memdev.c

+1 −0
Original line number Diff line number Diff line
@@ -344,6 +344,7 @@ struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds) 
	 * needed as this is ordered with cdev_add() publishing the device.

	 */

	cxlmd->cxlds = cxlds;

	cxlds->cxlmd = cxlmd;



	cdev = &cxlmd->cdev;

	rc = cdev_device_add(cdev, dev);

drivers/cxl/core/pci.c

+1 −2
Original line number Diff line number Diff line
@@ -54,8 +54,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data) 
		dev_dbg(&port->dev, "failed to find component registers\n");



	port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);

	dport = devm_cxl_add_dport(port, &pdev->dev, port_num,

				   cxl_regmap_to_base(pdev, &map));

	dport = devm_cxl_add_dport(port, &pdev->dev, port_num, map.resource);

	if (IS_ERR(dport)) {

		ctx->error = PTR_ERR(dport);

		return PTR_ERR(dport);

drivers/cxl/core/port.c

+1 −1
Original line number Diff line number Diff line
@@ -1292,7 +1292,7 @@ static resource_size_t find_component_registers(struct device *dev) 
	pdev = to_pci_dev(dev);



	cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);

	return cxl_regmap_to_base(pdev, &map);

	return map.resource;

}



static int add_port_attach_ep(struct cxl_memdev *cxlmd,