Loading arch/arm/mach-omap2/cm2xxx.c +0 −97 Original line number Diff line number Diff line Loading @@ -95,103 +95,6 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void) _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE); } /* * APLL control */ static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) { u32 v; v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); v &= ~mask; v |= m << __ffs(mask); omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); } void omap2xxx_cm_set_apll54_disable_autoidle(void) { _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, OMAP24XX_AUTO_54M_MASK); } void omap2xxx_cm_set_apll54_auto_low_power_stop(void) { _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, OMAP24XX_AUTO_54M_MASK); } void omap2xxx_cm_set_apll96_disable_autoidle(void) { _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, OMAP24XX_AUTO_96M_MASK); } void omap2xxx_cm_set_apll96_auto_low_power_stop(void) { _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, OMAP24XX_AUTO_96M_MASK); } /* Enable an APLL if off */ static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit) { u32 v, m; m = EN_APLL_LOCKED << enable_bit; v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); if (v & m) return 0; /* apll already enabled */ v |= m; omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); omap2xxx_cm_wait_module_ready(0, PLL_MOD, 1, status_bit); /* * REVISIT: Should we return an error code if * omap2xxx_cm_wait_module_ready() fails? */ return 0; } /* Stop APLL */ static void _omap2xxx_apll_disable(u8 enable_bit) { u32 v; v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); v &= ~(EN_APLL_LOCKED << enable_bit); omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); } /* Enable an APLL if off */ int omap2xxx_cm_apll54_enable(void) { return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT, OMAP24XX_ST_54M_APLL_SHIFT); } /* Enable an APLL if off */ int omap2xxx_cm_apll96_enable(void) { return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT, OMAP24XX_ST_96M_APLL_SHIFT); } /* Stop APLL */ void omap2xxx_cm_apll54_disable(void) { _omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT); } /* Stop APLL */ void omap2xxx_cm_apll96_disable(void) { _omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT); } /** * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components * @idlest_reg: CM_IDLEST* virtual address Loading arch/arm/mach-omap2/cm2xxx.h +0 −5 Original line number Diff line number Diff line Loading @@ -46,11 +46,6 @@ extern void omap2xxx_cm_set_dpll_disable_autoidle(void); extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); extern void omap2xxx_cm_set_apll54_disable_autoidle(void); extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void); extern void omap2xxx_cm_set_apll96_disable_autoidle(void); extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id, u8 idlest_shift); extern int omap2xxx_cm_fclks_active(void); Loading arch/arm/mach-omap2/cm2xxx_3xxx.h +0 −5 Original line number Diff line number Diff line Loading @@ -93,11 +93,6 @@ static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); } extern int omap2xxx_cm_apll54_enable(void); extern void omap2xxx_cm_apll54_disable(void); extern int omap2xxx_cm_apll96_enable(void); extern void omap2xxx_cm_apll96_disable(void); #endif /* CM register bits shared between 24XX and 3430 */ Loading Loading
arch/arm/mach-omap2/cm2xxx.c +0 −97 Original line number Diff line number Diff line Loading @@ -95,103 +95,6 @@ void omap2xxx_cm_set_dpll_auto_low_power_stop(void) _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE); } /* * APLL control */ static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) { u32 v; v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); v &= ~mask; v |= m << __ffs(mask); omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); } void omap2xxx_cm_set_apll54_disable_autoidle(void) { _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, OMAP24XX_AUTO_54M_MASK); } void omap2xxx_cm_set_apll54_auto_low_power_stop(void) { _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, OMAP24XX_AUTO_54M_MASK); } void omap2xxx_cm_set_apll96_disable_autoidle(void) { _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, OMAP24XX_AUTO_96M_MASK); } void omap2xxx_cm_set_apll96_auto_low_power_stop(void) { _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, OMAP24XX_AUTO_96M_MASK); } /* Enable an APLL if off */ static int _omap2xxx_apll_enable(u8 enable_bit, u8 status_bit) { u32 v, m; m = EN_APLL_LOCKED << enable_bit; v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); if (v & m) return 0; /* apll already enabled */ v |= m; omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); omap2xxx_cm_wait_module_ready(0, PLL_MOD, 1, status_bit); /* * REVISIT: Should we return an error code if * omap2xxx_cm_wait_module_ready() fails? */ return 0; } /* Stop APLL */ static void _omap2xxx_apll_disable(u8 enable_bit) { u32 v; v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); v &= ~(EN_APLL_LOCKED << enable_bit); omap2_cm_write_mod_reg(v, PLL_MOD, CM_CLKEN); } /* Enable an APLL if off */ int omap2xxx_cm_apll54_enable(void) { return _omap2xxx_apll_enable(OMAP24XX_EN_54M_PLL_SHIFT, OMAP24XX_ST_54M_APLL_SHIFT); } /* Enable an APLL if off */ int omap2xxx_cm_apll96_enable(void) { return _omap2xxx_apll_enable(OMAP24XX_EN_96M_PLL_SHIFT, OMAP24XX_ST_96M_APLL_SHIFT); } /* Stop APLL */ void omap2xxx_cm_apll54_disable(void) { _omap2xxx_apll_disable(OMAP24XX_EN_54M_PLL_SHIFT); } /* Stop APLL */ void omap2xxx_cm_apll96_disable(void) { _omap2xxx_apll_disable(OMAP24XX_EN_96M_PLL_SHIFT); } /** * omap2xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components * @idlest_reg: CM_IDLEST* virtual address Loading
arch/arm/mach-omap2/cm2xxx.h +0 −5 Original line number Diff line number Diff line Loading @@ -46,11 +46,6 @@ extern void omap2xxx_cm_set_dpll_disable_autoidle(void); extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void); extern void omap2xxx_cm_set_apll54_disable_autoidle(void); extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void); extern void omap2xxx_cm_set_apll96_disable_autoidle(void); extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void); int omap2xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id, u8 idlest_shift); extern int omap2xxx_cm_fclks_active(void); Loading
arch/arm/mach-omap2/cm2xxx_3xxx.h +0 −5 Original line number Diff line number Diff line Loading @@ -93,11 +93,6 @@ static inline u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); } extern int omap2xxx_cm_apll54_enable(void); extern void omap2xxx_cm_apll54_disable(void); extern int omap2xxx_cm_apll96_enable(void); extern void omap2xxx_cm_apll96_disable(void); #endif /* CM register bits shared between 24XX and 3430 */ Loading