Loading drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +13 −16 Original line number Diff line number Diff line Loading @@ -3,6 +3,7 @@ #include <core/subdev.h> struct nvkm_pmu { const struct nvkm_pmu_func *func; struct nvkm_subdev subdev; struct { Loading @@ -20,24 +21,20 @@ struct nvkm_pmu { u32 message; u32 data[2]; } recv; int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32); void (*pgob)(struct nvkm_pmu *, bool); }; static inline struct nvkm_pmu * nvkm_pmu(void *obj) { return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU); } extern struct nvkm_oclass *gt215_pmu_oclass; extern struct nvkm_oclass *gf100_pmu_oclass; extern struct nvkm_oclass *gf110_pmu_oclass; extern struct nvkm_oclass *gk104_pmu_oclass; extern struct nvkm_oclass *gk110_pmu_oclass; extern struct nvkm_oclass *gk208_pmu_oclass; extern struct nvkm_oclass *gk20a_pmu_oclass; int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); int gt215_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gf100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gf119_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk104_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); /* interface to MEMX process running on PMU */ struct nvkm_memx; Loading drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +23 −23 Original line number Diff line number Diff line Loading @@ -1111,7 +1111,7 @@ nva3_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1144,7 +1144,7 @@ nva5_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1176,7 +1176,7 @@ nva8_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1270,7 +1270,7 @@ nvaf_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1304,7 +1304,7 @@ nvc0_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1339,7 +1339,7 @@ nvc1_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1373,7 +1373,7 @@ nvc3_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1407,7 +1407,7 @@ nvc4_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1442,7 +1442,7 @@ nvc8_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1477,7 +1477,7 @@ nvce_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1512,7 +1512,7 @@ nvcf_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1578,7 +1578,7 @@ nvd9_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf110_pmu_new, .pmu = gf119_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1612,7 +1612,7 @@ nve4_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk104_pmu_new, .pmu = gk104_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1648,7 +1648,7 @@ nve6_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk104_pmu_new, .pmu = gk104_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1684,7 +1684,7 @@ nve7_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf110_pmu_new, .pmu = gf119_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1715,7 +1715,7 @@ nvea_chipset = { .ltc = gk104_ltc_new, .mc = gk20a_mc_new, .mmu = gf100_mmu_new, // .pmu = gk20a_pmu_new, .pmu = gk20a_pmu_new, // .timer = gk20a_timer_new, // .volt = gk20a_volt_new, // .ce[2] = gk104_ce2_new, Loading Loading @@ -1744,7 +1744,7 @@ nvf0_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk110_pmu_new, .pmu = gk110_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1780,7 +1780,7 @@ nvf1_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk110_pmu_new, .pmu = gk110_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1816,7 +1816,7 @@ nv106_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gk208_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1851,7 +1851,7 @@ nv108_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gk208_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1886,7 +1886,7 @@ nv117_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gm107_pmu_new, // .therm = gm107_therm_new, // .timer = gk20a_timer_new, // .ce[0] = gk104_ce0_new, Loading Loading @@ -1915,7 +1915,7 @@ nv124_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gm107_pmu_new, // .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, Loading Loading @@ -1944,7 +1944,7 @@ nv126_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gm107_pmu_new, // .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, Loading drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +0 −8 Original line number Diff line number Diff line Loading @@ -30,7 +30,6 @@ gf100_identify(struct nvkm_device *device) case 0xc0: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -47,7 +46,6 @@ gf100_identify(struct nvkm_device *device) case 0xc4: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -64,7 +62,6 @@ gf100_identify(struct nvkm_device *device) case 0xc3: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -80,7 +77,6 @@ gf100_identify(struct nvkm_device *device) case 0xce: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -97,7 +93,6 @@ gf100_identify(struct nvkm_device *device) case 0xcf: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -113,7 +108,6 @@ gf100_identify(struct nvkm_device *device) case 0xc1: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -129,7 +123,6 @@ gf100_identify(struct nvkm_device *device) case 0xc8: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -146,7 +139,6 @@ gf100_identify(struct nvkm_device *device) case 0xd9: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +0 −8 Original line number Diff line number Diff line Loading @@ -30,7 +30,6 @@ gk104_identify(struct nvkm_device *device) case 0xe4: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -48,7 +47,6 @@ gk104_identify(struct nvkm_device *device) case 0xe7: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -66,7 +64,6 @@ gk104_identify(struct nvkm_device *device) case 0xe6: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -90,12 +87,10 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; break; case 0xf0: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -113,7 +108,6 @@ gk104_identify(struct nvkm_device *device) case 0xf1: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -131,7 +125,6 @@ gk104_identify(struct nvkm_device *device) case 0x106: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; Loading @@ -148,7 +141,6 @@ gk104_identify(struct nvkm_device *device) case 0x108: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; Loading drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +0 −3 Original line number Diff line number Diff line Loading @@ -30,7 +30,6 @@ gm100_identify(struct nvkm_device *device) case 0x117: device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; Loading Loading @@ -58,7 +57,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif Loading @@ -83,7 +81,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif Loading Loading
drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +13 −16 Original line number Diff line number Diff line Loading @@ -3,6 +3,7 @@ #include <core/subdev.h> struct nvkm_pmu { const struct nvkm_pmu_func *func; struct nvkm_subdev subdev; struct { Loading @@ -20,24 +21,20 @@ struct nvkm_pmu { u32 message; u32 data[2]; } recv; int (*message)(struct nvkm_pmu *, u32[2], u32, u32, u32, u32); void (*pgob)(struct nvkm_pmu *, bool); }; static inline struct nvkm_pmu * nvkm_pmu(void *obj) { return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_PMU); } extern struct nvkm_oclass *gt215_pmu_oclass; extern struct nvkm_oclass *gf100_pmu_oclass; extern struct nvkm_oclass *gf110_pmu_oclass; extern struct nvkm_oclass *gk104_pmu_oclass; extern struct nvkm_oclass *gk110_pmu_oclass; extern struct nvkm_oclass *gk208_pmu_oclass; extern struct nvkm_oclass *gk20a_pmu_oclass; int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); int gt215_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gf100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gf119_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk104_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk110_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk208_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gk20a_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gm107_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); /* interface to MEMX process running on PMU */ struct nvkm_memx; Loading
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +23 −23 Original line number Diff line number Diff line Loading @@ -1111,7 +1111,7 @@ nva3_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1144,7 +1144,7 @@ nva5_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1176,7 +1176,7 @@ nva8_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1270,7 +1270,7 @@ nvaf_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, // .pmu = gt215_pmu_new, .pmu = gt215_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1304,7 +1304,7 @@ nvc0_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1339,7 +1339,7 @@ nvc1_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1373,7 +1373,7 @@ nvc3_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1407,7 +1407,7 @@ nvc4_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1442,7 +1442,7 @@ nvc8_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1477,7 +1477,7 @@ nvce_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1512,7 +1512,7 @@ nvcf_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf100_pmu_new, .pmu = gf100_pmu_new, // .therm = gt215_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1578,7 +1578,7 @@ nvd9_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf110_pmu_new, .pmu = gf119_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1612,7 +1612,7 @@ nve4_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk104_pmu_new, .pmu = gk104_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1648,7 +1648,7 @@ nve6_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk104_pmu_new, .pmu = gk104_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1684,7 +1684,7 @@ nve7_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gf110_pmu_new, .pmu = gf119_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1715,7 +1715,7 @@ nvea_chipset = { .ltc = gk104_ltc_new, .mc = gk20a_mc_new, .mmu = gf100_mmu_new, // .pmu = gk20a_pmu_new, .pmu = gk20a_pmu_new, // .timer = gk20a_timer_new, // .volt = gk20a_volt_new, // .ce[2] = gk104_ce2_new, Loading Loading @@ -1744,7 +1744,7 @@ nvf0_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk110_pmu_new, .pmu = gk110_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1780,7 +1780,7 @@ nvf1_chipset = { .mc = gf106_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk110_pmu_new, .pmu = gk110_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1816,7 +1816,7 @@ nv106_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gk208_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1851,7 +1851,7 @@ nv108_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gk208_pmu_new, // .therm = gf110_therm_new, // .timer = nv04_timer_new, // .volt = nv40_volt_new, Loading Loading @@ -1886,7 +1886,7 @@ nv117_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gm107_pmu_new, // .therm = gm107_therm_new, // .timer = gk20a_timer_new, // .ce[0] = gk104_ce0_new, Loading Loading @@ -1915,7 +1915,7 @@ nv124_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gm107_pmu_new, // .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, Loading Loading @@ -1944,7 +1944,7 @@ nv126_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, // .pmu = gk208_pmu_new, .pmu = gm107_pmu_new, // .timer = gk20a_timer_new, // .ce[0] = gm204_ce0_new, // .ce[1] = gm204_ce1_new, Loading
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c +0 −8 Original line number Diff line number Diff line Loading @@ -30,7 +30,6 @@ gf100_identify(struct nvkm_device *device) case 0xc0: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -47,7 +46,6 @@ gf100_identify(struct nvkm_device *device) case 0xc4: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -64,7 +62,6 @@ gf100_identify(struct nvkm_device *device) case 0xc3: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -80,7 +77,6 @@ gf100_identify(struct nvkm_device *device) case 0xce: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -97,7 +93,6 @@ gf100_identify(struct nvkm_device *device) case 0xcf: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -113,7 +108,6 @@ gf100_identify(struct nvkm_device *device) case 0xc1: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -129,7 +123,6 @@ gf100_identify(struct nvkm_device *device) case 0xc8: device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading @@ -146,7 +139,6 @@ gf100_identify(struct nvkm_device *device) case 0xd9: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass; Loading
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c +0 −8 Original line number Diff line number Diff line Loading @@ -30,7 +30,6 @@ gk104_identify(struct nvkm_device *device) case 0xe4: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -48,7 +47,6 @@ gk104_identify(struct nvkm_device *device) case 0xe7: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -66,7 +64,6 @@ gk104_identify(struct nvkm_device *device) case 0xe6: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -90,12 +87,10 @@ gk104_identify(struct nvkm_device *device) device->oclass[NVDEV_ENGINE_CE2 ] = &gk104_ce2_oclass; device->oclass[NVDEV_ENGINE_PM ] = gk104_pm_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &gk20a_volt_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk20a_pmu_oclass; break; case 0xf0: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -113,7 +108,6 @@ gk104_identify(struct nvkm_device *device) case 0xf1: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk104_fifo_oclass; Loading @@ -131,7 +125,6 @@ gk104_identify(struct nvkm_device *device) case 0x106: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; Loading @@ -148,7 +141,6 @@ gk104_identify(struct nvkm_device *device) case 0x108: device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk208_fifo_oclass; Loading
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +0 −3 Original line number Diff line number Diff line Loading @@ -30,7 +30,6 @@ gm100_identify(struct nvkm_device *device) case 0x117: device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; Loading Loading @@ -58,7 +57,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif Loading @@ -83,7 +81,6 @@ gm100_identify(struct nvkm_device *device) device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass; #endif device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass; #if 0 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; #endif Loading