Commit e49936d2 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'omap-for-v5.13/dts-genpd-signed' of... 

Merge tag 'omap-for-v5.13/dts-genpd-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

Devicetree changes for omaps for genpd support for v5.13

In order to move omap4/5 and dra7 to probe with devicetree data and genpd,
we need to add the missing interconnect target module configuration for
the drivers that do not still have it. This is similar to what we have
already done earlier for am3 and 4 earlier.

These patches are very much similar for all the three SoCs here. The dra7
changes were already available for v5.12 merge window, but were considered
too late to add for v5.12. The patches for omap4 and 5 follow the same
pattern, except for PCIe that is available only on dra7.

We do the changes one driver at a time, and still keep the legacy property
for "ti,hwmods" mostly around, except for cases when already not needed.
We will be dropping the custom property and related legacy data in a
follow-up series.

* tag 'omap-for-v5.13/dts-genpd-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (53 commits)
  ARM: dts: Configure simple-pm-bus for omap5 l3
  ARM: dts: Configure simple-pm-bus for omap5 l4_cfg
  ARM: dts: Configure simple-pm-bus for omap5 l4_per
  ARM: dts: Configure simple-pm-bus for omap5 l4_wkup
  ARM: dts: Move omap5 l3-noc to a separate node
  ARM: dts: Move omap5 mmio-sram out of l3 interconnect
  ARM: dts: Configure interconnect target module for omap5 sata
  ARM: dts: Configure interconnect target module for omap5 gpmc
  ARM: dts: Configure interconnect target module for omap5 mpu
  ARM: dts: Configure interconnect target module for omap5 emif
  ARM: dts: Configure interconnect target module for omap5 dmm
  ARM: dts: Prepare for simple-pm-bus for omap4 l3
  ARM: dts: Configure simple-pm-bus for omap4 l4_cfg
  ARM: dts: Configure simple-pm-bus for omap4 l4_per
  ARM: dts: Configure simple-pm-bus for omap4 l4_wkup
  ARM: dts: Move omap4 l3-noc to a separate node
  ARM: dts: Move omap4 mmio-sram out of l3 interconnect
  ARM: dts: Configure interconnect target module for omap4 mpu
  ARM: dts: Configure interconnect target module for omap4 debugss
  ARM: dts: Configure interconnect target module for omap4 emif
  ...

Link: https://lore.kernel.org/r/pull-1617004205-537424@atomide.com-2


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f374f25a 083516ad

arch/arm/boot/dts/am33xx.dtsi

+3 −0
Original line number Diff line number Diff line
@@ -40,6 +40,9 @@ aliases { 
		ethernet1 = &cpsw_emac1;

		spi0 = &spi0;

		spi1 = &spi1;

		mmc0 = &mmc1;

		mmc1 = &mmc2;

		mmc2 = &mmc3;

	};



	cpus {

arch/arm/boot/dts/dra7-l4.dtsi

+57 −19
Original line number Diff line number Diff line 
&l4_cfg {						/* 0x4a000000 */

	compatible = "ti,dra7-l4-cfg", "simple-bus";

	compatible = "ti,dra7-l4-cfg", "simple-pm-bus";

	power-domains = <&prm_coreaon>;

	clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x4a000000 0x800>,

	      <0x4a000800 0x800>,

	      <0x4a001000 0x1000>;
@@ -11,7 +14,7 @@ &l4_cfg { /* 0x4a000000 */ 
		 <0x00200000 0x4a200000 0x100000>;	/* segment 2 */



	segment@0 {					/* 0x4a000000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -493,7 +496,7 @@ hwspinlock: spinlock@0 { 
	};



	segment@100000 {					/* 0x4a100000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00002000 0x00102000 0x001000>,	/* ap 27 */
@@ -572,11 +575,34 @@ target-module@8000 { /* 0x4a108000, ap 29 1e.0 */ 
		};



		target-module@40000 {			/* 0x4a140000, ap 31 06.0 */

			compatible = "ti,sysc";

			status = "disabled";

			#address-cells = <1>;

			compatible = "ti,sysc-omap4", "ti,sysc";

			ti,hwmods = "sata";

			reg = <0x400fc 4>,

			      <0x41100 4>;

			reg-names = "rev", "sysc";

			ti,sysc-midle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>,

					<SYSC_IDLE_SMART_WKUP>;

			power-domains = <&prm_l3init>;

			clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 0>;

			clock-names = "fck";

			#size-cells = <1>;

			#address-cells = <1>;

			ranges = <0x0 0x40000 0x10000>;



			sata: sata@0 {

				compatible = "snps,dwc-ahci";

				reg = <0 0x1100>, <0x1100 0x8>;

				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

				phys = <&sata_phy>;

				phy-names = "sata-phy";

				clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;

				ports-implemented = <0x1>;

			};

		};



		target-module@51000 {			/* 0x4a151000, ap 33 50.0 */
@@ -789,7 +815,7 @@ target-module@87000 { /* 0x4a187000, ap 75 74.0 */ 
	};



	segment@200000 {					/* 0x4a200000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00018000 0x00218000 0x001000>,	/* ap 43 */
@@ -1006,7 +1032,10 @@ target-module@36000 { /* 0x4a236000, ap 119 62.0 */ 
};



&l4_per1 {						/* 0x48000000 */

	compatible = "ti,dra7-l4-per1", "simple-bus";

	compatible = "ti,dra7-l4-per1", "simple-pm-bus";

	power-domains = <&prm_l4per>;

	clocks = <&l4per_clkctrl DRA7_L4PER_L4_PER1_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x48000000 0x800>,

	      <0x48000800 0x800>,

	      <0x48001000 0x400>,
@@ -1020,7 +1049,7 @@ &l4_per1 { /* 0x48000000 */ 
		 <0x00200000 0x48200000 0x200000>;	/* segment 1 */



	segment@0 {					/* 0x48000000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -2269,14 +2298,17 @@ target-module@d5000 { /* 0x480d5000, ap 73 30.0 */ 
	};



	segment@200000 {					/* 0x48200000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

	};

};



&l4_per2 {						/* 0x48400000 */

	compatible = "ti,dra7-l4-per2", "simple-bus";

	compatible = "ti,dra7-l4-per2", "simple-pm-bus";

	power-domains = <&prm_l4per>;

	clocks = <&l4per2_clkctrl DRA7_L4PER2_L4_PER2_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x48400000 0x800>,

	      <0x48400800 0x800>,

	      <0x48401000 0x400>,
@@ -2296,7 +2328,7 @@ &l4_per2 { /* 0x48400000 */ 
		 <0x48454000 0x48454000 0x400000>;	/* L3 data port */



	segment@0 {					/* 0x48400000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -3094,7 +3126,10 @@ cpts { 
};



&l4_per3 {						/* 0x48800000 */

	compatible = "ti,dra7-l4-per3", "simple-bus";

	compatible = "ti,dra7-l4-per3", "simple-pm-bus";

	power-domains = <&prm_l4per>;

	clocks = <&l4per3_clkctrl DRA7_L4PER3_L4_PER3_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x48800000 0x800>,

	      <0x48800800 0x800>,

	      <0x48801000 0x400>,
@@ -3106,7 +3141,7 @@ &l4_per3 { /* 0x48800000 */ 
	ranges = <0x00000000 0x48800000 0x200000>;	/* segment 0 */



	segment@0 {					/* 0x48800000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -4205,7 +4240,10 @@ vpe: vpe@0 { 
};



&l4_wkup {						/* 0x4ae00000 */

	compatible = "ti,dra7-l4-wkup", "simple-bus";

	compatible = "ti,dra7-l4-wkup", "simple-pm-bus";

	power-domains = <&prm_wkupaon>;

	clocks = <&wkupaon_clkctrl DRA7_WKUPAON_L4_WKUP_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x4ae00000 0x800>,

	      <0x4ae00800 0x800>,

	      <0x4ae01000 0x1000>;
@@ -4218,7 +4256,7 @@ &l4_wkup { /* 0x4ae00000 */ 
		 <0x00030000 0x4ae30000 0x010000>;	/* segment 3 */



	segment@0 {					/* 0x4ae00000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -4295,7 +4333,7 @@ scm_wkup: scm_conf@0 { 
	};



	segment@10000 {					/* 0x4ae10000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00010000 0x001000>,	/* ap 5 */
@@ -4405,7 +4443,7 @@ target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */ 
	};



	segment@20000 {					/* 0x4ae20000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00006000 0x00026000 0x001000>,	/* ap 13 */
@@ -4511,7 +4549,7 @@ target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */ 
	};



	segment@30000 {					/* 0x4ae30000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0000c000 0x0003c000 0x002000>,	/* ap 30 */

arch/arm/boot/dts/dra7.dtsi

+148 −67
Original line number Diff line number Diff line
@@ -124,18 +124,6 @@ opp_high@1500000000 { 
		};

	};



	/*

	 * The soc node represents the soc top level view. It is used for IPs

	 * that are not memory mapped in the MPU view or for the MPU itself.

	 */

	soc {

		compatible = "ti,omap-infra";

		mpu {

			compatible = "ti,omap5-mpu";

			ti,hwmods = "mpu";

		};

	};



	/*

	 * XXX: Use a flat representation of the SOC interconnect.

	 * The real OMAP interconnect network is quite complex.
@@ -144,16 +132,22 @@ mpu { 
	 * hierarchy.

	 */

	ocp: ocp {

		compatible = "ti,dra7-l3-noc", "simple-bus";

		compatible = "simple-pm-bus";

		power-domains = <&prm_core>;

		clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,

			 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x0 0xc0000000>;

		dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;

		ti,hwmods = "l3_main_1", "l3_main_2";

		reg = <0x0 0x44000000 0x0 0x1000000>,

		      <0x0 0x45000000 0x0 0x1000>;



		l3-noc@44000000 {

			compatible = "ti,dra7-l3-noc";

			reg = <0x44000000 0x1000>,

			      <0x45000000 0x1000>;

			interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

					      <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		};



		l4_cfg: interconnect@4a000000 {

		};
@@ -161,31 +155,61 @@ l4_wkup: interconnect@4ae00000 { 
		};

		l4_per1: interconnect@48000000 {

		};



		target-module@48210000 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			power-domains = <&prm_mpu>;

			clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x48210000 0x1f0000>;



			mpu {

				compatible = "ti,omap5-mpu";

			};

		};



		l4_per2: interconnect@48400000 {

		};

		l4_per3: interconnect@48800000 {

		};



		axi@0 {

			compatible = "simple-bus";

		/*

		 * Register access seems to have complex dependencies and also

		 * seems to need an enabled phy. See the TRM chapter for "Table

		 * 26-678. Main Sequence PCIe Controller Global Initialization"

		 * and also dra7xx_pcie_probe().

		 */

		axi0: target-module@51000000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			power-domains = <&prm_l3init>;

			resets = <&prm_l3init 0>;

			reset-names = "rstctrl";

			clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,

				 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,

				 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;

			clock-names = "fck", "phy-clk", "phy-clk-div";

			#size-cells = <1>;

			#address-cells = <1>;

			ranges = <0x51000000 0x51000000 0x3000

				  0x0	     0x20000000 0x10000000>;

			ranges = <0x51000000 0x51000000 0x3000>,

				 <0x20000000 0x20000000 0x10000000>;

			dma-ranges;

			/**

			 * To enable PCI endpoint mode, disable the pcie1_rc

			 * node and enable pcie1_ep mode.

			 */

			pcie1_rc: pcie@51000000 {

				reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;

				reg = <0x51000000 0x2000>,

				      <0x51002000 0x14c>,

				      <0x20001000 0x2000>;

				reg-names = "rc_dbics", "ti_conf", "config";

				interrupts = <0 232 0x4>, <0 233 0x4>;

				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				ranges = <0x81000000 0 0          0x03000 0 0x00010000

					  0x82000000 0 0x20013000 0x13000 0 0xffed000>;

				ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,

					 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;

				bus-range = <0x00 0xff>;

				#interrupt-cells = <1>;

				num-lanes = <1>;
@@ -209,7 +233,10 @@ pcie1_intc: interrupt-controller { 
			};



			pcie1_ep: pcie_ep@51000000 {

				reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;

				reg = <0x51000000 0x28>,

				      <0x51002000 0x14c>,

				      <0x51001000 0x28>,

				      <0x20001000 0x10000000>;

				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";

				interrupts = <0 232 0x4>;

				num-lanes = <1>;
@@ -224,23 +251,38 @@ pcie1_ep: pcie_ep@51000000 { 
			};

		};



		axi@1 {

			compatible = "simple-bus";

		/*

		 * Register access seems to have complex dependencies and also

		 * seems to need an enabled phy. See the TRM chapter for "Table

		 * 26-678. Main Sequence PCIe Controller Global Initialization"

		 * and also dra7xx_pcie_probe().

		 */

		axi1: target-module@51800000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,

				 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,

				 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;

			clock-names = "fck", "phy-clk", "phy-clk-div";

			power-domains = <&prm_l3init>;

			resets = <&prm_l3init 1>;

			reset-names = "rstctrl";

			#size-cells = <1>;

			#address-cells = <1>;

			ranges = <0x51800000 0x51800000 0x3000

				  0x0	     0x30000000 0x10000000>;

			ranges = <0x51800000 0x51800000 0x3000>,

				 <0x30000000 0x30000000 0x10000000>;

			dma-ranges;

			status = "disabled";

			pcie2_rc: pcie@51800000 {

				reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;

				reg = <0x51800000 0x2000>,

				      <0x51802000 0x14c>,

				      <0x30001000 0x2000>;

				reg-names = "rc_dbics", "ti_conf", "config";

				interrupts = <0 355 0x4>, <0 356 0x4>;

				#address-cells = <3>;

				#size-cells = <2>;

				device_type = "pci";

				ranges = <0x81000000 0 0          0x03000 0 0x00010000

					  0x82000000 0 0x30013000 0x13000 0 0xffed000>;

				ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,

					 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;

				bus-range = <0x00 0xff>;

				#interrupt-cells = <1>;

				num-lanes = <1>;
@@ -336,8 +378,15 @@ dra7_iodelay_core: padconf@4844a000 { 


		target-module@43300000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x43300000 0x4>;

			reg-names = "rev";

			reg = <0x43300000 0x4>,

			      <0x43300010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-midle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;
@@ -369,8 +418,15 @@ edma: dma@0 { 


		target-module@43400000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x43400000 0x4>;

			reg-names = "rev";

			reg = <0x43400000 0x4>,

			      <0x43400010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-midle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;
@@ -387,8 +443,15 @@ edma_tptc0: dma@0 { 


		target-module@43500000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			reg = <0x43500000 0x4>;

			reg-names = "rev";

			reg = <0x43500000 0x4>,

			      <0x43500010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-midle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;
@@ -403,11 +466,24 @@ edma_tptc1: dma@0 { 
			};

		};



		dmm@4e000000 {

		target-module@4e000000 {

			compatible = "ti,sysc-omap2", "ti,sysc";

			ti,hwmods = "dmm";

			reg = <0x4e000000 0x4>,

			      <0x4e000010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ranges = <0x0 0x4e000000 0x2000000>;

			#size-cells = <1>;

			#address-cells = <1>;



			dmm@0 {

				compatible = "ti,omap5-dmm";

			reg = <0x4e000000 0x800>;

				reg = <0 0x800>;

				interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "dmm";

			};

		};



		ipu1: ipu@58820000 {
@@ -694,32 +770,37 @@ abb_gpu: regulator-abb-gpu { 
			>;

		};



		qspi: spi@4b300000 {

		target-module@4b300000 {

			compatible = "ti,sysc-omap4", "ti,sysc";

			ti,hwmods = "qspi";

			reg = <0x4b300000 0x4>,

			      <0x4b300010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>,

					<SYSC_IDLE_SMART_WKUP>;

			clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x4b300000 0x1000>,

				 <0x5c000000 0x5c000000 0x4000000>;



			qspi: spi@0 {

				compatible = "ti,dra7xxx-qspi";

			reg = <0x4b300000 0x100>,

				reg = <0 0x100>,

				      <0x5c000000 0x4000000>;

				reg-names = "qspi_base", "qspi_mmap";

				syscon-chipselects = <&scm_conf 0x558>;

				#address-cells = <1>;

				#size-cells = <0>;

			ti,hwmods = "qspi";

				clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;

				clock-names = "fck";

				num-cs = <4>;

				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;

				status = "disabled";

			};



		/* OCP2SCP3 */

		sata: sata@4a141100 {

			compatible = "snps,dwc-ahci";

			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;

			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;

			phys = <&sata_phy>;

			phy-names = "sata-phy";

			clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;

			ti,hwmods = "sata";

			ports-implemented = <0x1>;

		};



		/* OCP2SCP1 */

arch/arm/boot/dts/omap4-l4.dtsi

+24 −15
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

&l4_cfg {						/* 0x4a000000 */

	compatible = "ti,omap4-l4-cfg", "simple-bus";

	compatible = "ti,omap4-l4-cfg", "simple-pm-bus";

	power-domains = <&prm_core>;

	clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x4a000000 0x800>,

	      <0x4a000800 0x800>,

	      <0x4a001000 0x1000>;
@@ -16,7 +19,7 @@ &l4_cfg { /* 0x4a000000 */ 
		 <0x00300000 0x4a300000 0x080000>;	/* segment 6 */



	segment@0 {					/* 0x4a000000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -347,7 +350,7 @@ mmu_dsp: mmu@0 { 
	};



	segment@80000 {					/* 0x4a080000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00059000 0x000d9000 0x001000>,	/* ap 13 */
@@ -639,7 +642,7 @@ hwspinlock: spinlock@0 { 
	};



	segment@100000 {					/* 0x4a100000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00100000 0x001000>,	/* ap 21 */
@@ -741,13 +744,13 @@ target-module@a000 { /* 0x4a10a000, ap 65 50.0 */ 
	};



	segment@180000 {					/* 0x4a180000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

	};



	segment@200000 {					/* 0x4a200000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0001e000 0x0021e000 0x001000>,	/* ap 31 */
@@ -903,13 +906,13 @@ target-module@2a000 { /* 0x4a22a000, ap 57 48.0 */ 
	};



	segment@280000 {					/* 0x4a280000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

	};



	l4_cfg_segment_300000: segment@300000 {			/* 0x4a300000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00300000 0x020000>,	/* ap 67 */
@@ -944,7 +947,10 @@ l4_cfg_target_0: target-module@0 { /* 0x4a300000, ap 67 14.0 */ 
};



&l4_wkup {						/* 0x4a300000 */

	compatible = "ti,omap4-l4-wkup", "simple-bus";

	compatible = "ti,omap4-l4-wkup", "simple-pm-bus";

	power-domains = <&prm_wkup>;

	clocks = <&l4_wkup_clkctrl OMAP4_L4_WKUP_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x4a300000 0x800>,

	      <0x4a300800 0x800>,

	      <0x4a301000 0x1000>;
@@ -956,7 +962,7 @@ &l4_wkup { /* 0x4a300000 */ 
		 <0x00020000 0x4a320000 0x010000>;	/* segment 2 */



	segment@0 {					/* 0x4a300000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -1062,7 +1068,7 @@ omap4_scm_wkup: scm@c000 { 
	};



	segment@10000 {					/* 0x4a310000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00010000 0x001000>,	/* ap 5 */
@@ -1231,7 +1237,7 @@ omap4_pmx_wkup: pinmux@40 { 
	};



	segment@20000 {					/* 0x4a320000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00006000 0x00026000 0x001000>,	/* ap 13 */
@@ -1284,7 +1290,10 @@ target-module@6000 { /* 0x4a326000, ap 13 28.0 */ 
};



&l4_per {						/* 0x48000000 */

	compatible = "ti,omap4-l4-per", "simple-bus";

	compatible = "ti,omap4-l4-per", "simple-pm-bus";

	power-domains = <&prm_l4per>;

	clocks = <&l4_per_clkctrl OMAP4_L4_PER_CLKCTRL 0>;

	clock-names = "fck";

	reg = <0x48000000 0x800>,

	      <0x48000800 0x800>,

	      <0x48001000 0x400>,
@@ -1298,7 +1307,7 @@ &l4_per { /* 0x48000000 */ 
		 <0x00200000 0x48200000 0x200000>;	/* segment 1 */



	segment@0 {					/* 0x48000000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00000000 0x00000000 0x000800>,	/* ap 0 */
@@ -2437,7 +2446,7 @@ mmc5: mmc@0 { 
	};



	segment@200000 {					/* 0x48200000 */

		compatible = "simple-bus";

		compatible = "simple-pm-bus";

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x00150000 0x00350000 0x001000>,	/* ap 77 */

arch/arm/boot/dts/omap4.dtsi

+118 −52
Original line number Diff line number Diff line
@@ -22,6 +22,11 @@ aliases { 
		i2c1 = &i2c2;

		i2c2 = &i2c3;

		i2c3 = &i2c4;

		mmc0 = &mmc1;

		mmc1 = &mmc2;

		mmc2 = &mmc3;

		mmc3 = &mmc4;

		mmc4 = &mmc5;

		serial0 = &uart1;

		serial1 = &uart2;

		serial2 = &uart3;
@@ -54,14 +59,12 @@ cpu@1 { 
	};



	/*

	 * Note that 4430 needs cross trigger interface (CTI) supported

	 * before we can configure the interrupts. This means sampling

	 * events are not supported for pmu. Note that 4460 does not use

	 * CTI, see also 4460.dtsi.

	 * Needed early by omap4_sram_init() for barrier, do not move to l3

	 * interconnect as simple-pm-bus probes at module_init() time.

	 */

	pmu {

		compatible = "arm,cortex-a9-pmu";

		ti,hwmods = "debugss";

	ocmcram: sram@40304000 {

		compatible = "mmio-sram";

		reg = <0x40304000 0xa000>; /* 40k */

	};



	gic: interrupt-controller@48241000 {
@@ -96,19 +99,6 @@ wakeupgen: interrupt-controller@48281000 { 
		interrupt-parent = <&gic>;

	};



	/*

	 * The soc node represents the soc top level view. It is used for IPs

	 * that are not memory mapped in the MPU view or for the MPU itself.

	 */

	soc {

		compatible = "ti,omap-infra";

		mpu {

			compatible = "ti,omap4-mpu";

			ti,hwmods = "mpu";

			sram = <&ocmcram>;

		};

	};



	/*

	 * XXX: Use a flat representation of the OMAP4 interconnect.

	 * The real OMAP interconnect network is quite complex.
@@ -117,16 +107,24 @@ mpu { 
	 * hierarchy.

	 */

	ocp {

		compatible = "ti,omap4-l3-noc", "simple-bus";

		compatible = "simple-bus";

		power-domains = <&prm_l4per>;

		clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,

			 <&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,

			 <&l3_instr_clkctrl OMAP4_L3_MAIN_3_CLKCTRL 0>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";



		l3-noc@44000000 {

			compatible = "ti,omap4-l3-noc";

			reg = <0x44000000 0x1000>,

			      <0x44800000 0x2000>,

			      <0x45000000 0x1000>;

			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;

		};



		l4_wkup: interconnect@4a300000 {

		};
@@ -137,12 +135,22 @@ l4_cfg: interconnect@4a000000 { 
		l4_per: interconnect@48000000 {

		};



		l4_abe: interconnect@40100000 {

		target-module@48210000 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			power-domains = <&prm_mpu>;

			clocks = <&mpuss_clkctrl OMAP4_MPU_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0 0x48210000 0x1f0000>;



			mpu {

				compatible = "ti,omap4-mpu";

				sram = <&ocmcram>;

			};

		};



		ocmcram: sram@40304000 {

			compatible = "mmio-sram";

			reg = <0x40304000 0xa000>; /* 40k */

		l4_abe: interconnect@40100000 {

		};



		target-module@50000000 {
@@ -198,6 +206,7 @@ target-module@52000000 { 
					<SYSC_IDLE_SMART>,

					<SYSC_IDLE_SMART_WKUP>;

			ti,sysc-delay-us = <2>;

			power-domains = <&prm_cam>;

			clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;
@@ -207,6 +216,27 @@ target-module@52000000 { 
			/* No child device binding, driver in staging */

		};



		/*

		 * Note that 4430 needs cross trigger interface (CTI) supported

		 * before we can configure the interrupts. This means sampling

		 * events are not supported for pmu. Note that 4460 does not use

		 * CTI, see also 4460.dtsi.

		 */

		target-module@54000000 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			ti,hwmods = "debugss";

			power-domains = <&prm_emu>;

			clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x54000000 0x1000000>;



			pmu: pmu {

				compatible = "arm,cortex-a9-pmu";

			};

		};



		target-module@55082000 {

			compatible = "ti,sysc-omap2", "ti,sysc";

			reg = <0x55082000 0x4>,
@@ -256,36 +286,71 @@ target-module@4012c000 { 
			/* No child device binding or driver in mainline */

		};



		dmm@4e000000 {

			compatible = "ti,omap4-dmm";

			reg = <0x4e000000 0x800>;

			interrupts = <0 113 0x4>;

		target-module@4e000000 {

			compatible = "ti,sysc-omap2", "ti,sysc";

			ti,hwmods = "dmm";

			reg = <0x4e000000 0x4>,

			      <0x4e000010 0x4>;

			reg-names = "rev", "sysc";

			ti,sysc-sidle = <SYSC_IDLE_FORCE>,

					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>;

			ranges = <0x0 0x4e000000 0x2000000>;

			#size-cells = <1>;

			#address-cells = <1>;



			dmm@0 {

				compatible = "ti,omap4-dmm";

				reg = <0 0x800>;

				interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;

			};

		};



		emif1: emif@4c000000 {

		target-module@4c000000 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			ti,hwmods = "emif1";

			reg = <0x4c000000 0x4>;

			reg-names = "rev";

			clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;

			clock-names = "fck";

			ti,no-idle;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x4c000000 0x1000000>;



			emif1: emif@0 {

				compatible = "ti,emif-4d";

			reg = <0x4c000000 0x100>;

				reg = <0 0x100>;

				interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "emif1";

			ti,no-idle-on-init;

				phy-type = <1>;

				hw-caps-read-idle-ctrl;

				hw-caps-ll-interface;

				hw-caps-temp-alert;

			};

		};



		emif2: emif@4d000000 {

		target-module@4d000000 {

			compatible = "ti,sysc-omap4-simple", "ti,sysc";

			ti,hwmods = "emif2";

			reg = <0x4d000000 0x4>;

			reg-names = "rev";

			clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;

			clock-names = "fck";

			ti,no-idle;

			#address-cells = <1>;

			#size-cells = <1>;

			ranges = <0x0 0x4d000000 0x1000000>;



			emif2: emif@0 {

				compatible = "ti,emif-4d";

			reg = <0x4d000000 0x100>;

				reg = <0 0x100>;

				interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;

			ti,hwmods = "emif2";

			ti,no-idle-on-init;

				phy-type = <1>;

				hw-caps-read-idle-ctrl;

				hw-caps-ll-interface;

				hw-caps-temp-alert;

			};

		};



		dsp: dsp {

			compatible = "ti,omap4-dsp";
@@ -435,6 +500,7 @@ sgx_module: target-module@56000000 { 
					<SYSC_IDLE_NO>,

					<SYSC_IDLE_SMART>,

					<SYSC_IDLE_SMART_WKUP>;

			power-domains = <&prm_gfx>;

			clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;

			clock-names = "fck";

			#address-cells = <1>;