Commit e690895a authored by Larry Finger's avatar Larry Finger Committed by Greg Kroah-Hartman
Browse files

staging: r8188eu: Remove macro ODM_SetBBReg 



It is essentially a duplicate of macro PHY_SetBBReg

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4b33d52a

drivers/staging/rtl8188eu/hal/HalPhyRf_8188e.c

+88 −88
Original line number Diff line number Diff line
@@ -428,17 +428,17 @@ odm_TXPowerTrackingCallback_ThermalMeter_8188E( 


						/* wtite new elements A, C, D to regC88 and regC9C, element B is always 0 */

						value32 = (ele_D<<22) | ((ele_C&0x3F)<<16) | ele_A;

						ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);

						PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);



						value32 = (ele_C&0x000003C0)>>6;

						ODM_SetBBReg(dm_odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);

						PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32);



						value32 = ((X * ele_D)>>7)&0x01;

						ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT28, value32);

						PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT28, value32);

					} else {

						ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)OFDM_index[1]]);

						ODM_SetBBReg(dm_odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);

						ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT28, 0x00);

						PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)OFDM_index[1]]);

						PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);

						PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00);

					}



					ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
@@ -485,19 +485,19 @@ phy_PathA_IQK_8188E(struct adapter *adapt, bool configPathB) 
	/* 1 Tx IQK */

	/* path-A IQK setting */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n"));

	ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);

	ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);

	ODM_SetBBReg(dm_odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);

	ODM_SetBBReg(dm_odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);

	PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);

	PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);

	PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);

	PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);



	/* LO calibration setting */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));

	ODM_SetBBReg(dm_odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);

	PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);



	/* One shot, path A LOK & IQK */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));

	ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);

	ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);

	PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);

	PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);



	/*  delay x ms */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
@@ -533,7 +533,7 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) 
	/* 1 Get TXIMR setting */

	/* modify RXIQK mode table */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));

	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);

	ODM_SetRFReg(dm_odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);

	ODM_SetRFReg(dm_odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);

	ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);
@@ -543,26 +543,26 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) 
	ODM_SetRFReg(dm_odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x980);

	ODM_SetRFReg(dm_odm, RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000);



	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);



	/* IQK setting */

	ODM_SetBBReg(dm_odm, rTx_IQK, bMaskDWord, 0x01007c00);

	ODM_SetBBReg(dm_odm, rRx_IQK, bMaskDWord, 0x81004800);

	PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);

	PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800);



	/* path-A IQK setting */

	ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);

	ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);

	ODM_SetBBReg(dm_odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);

	ODM_SetBBReg(dm_odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);

	PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);

	PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);

	PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f);

	PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160000);



	/* LO calibration setting */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));

	ODM_SetBBReg(dm_odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);

	PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);



	/* One shot, path A LOK & IQK */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));

	ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);

	ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);

	PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);

	PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);



	/*  delay x ms */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
@@ -589,36 +589,36 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) 
		return result;



	u4tmp = 0x80007C00 | (regE94&0x3FF0000)  | ((regE9C&0x3FF0000) >> 16);

	ODM_SetBBReg(dm_odm, rTx_IQK, bMaskDWord, u4tmp);

	PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, u4tmp);

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", ODM_GetBBReg(dm_odm, rTx_IQK, bMaskDWord), u4tmp));



	/* 1 RX IQK */

	/* modify RXIQK mode table */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));

	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);

	ODM_SetRFReg(dm_odm, RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0);

	ODM_SetRFReg(dm_odm, RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000);

	ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f);

	ODM_SetRFReg(dm_odm, RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa);

	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);



	/* IQK setting */

	ODM_SetBBReg(dm_odm, rRx_IQK, bMaskDWord, 0x01004800);

	PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x01004800);



	/* path-A IQK setting */

	ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);

	ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);

	ODM_SetBBReg(dm_odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);

	ODM_SetBBReg(dm_odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);

	PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c);

	PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c);

	PHY_SetBBReg(adapt, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);

	PHY_SetBBReg(adapt, rRx_IQK_PI_A, bMaskDWord, 0x28160c1f);



	/* LO calibration setting */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));

	ODM_SetBBReg(dm_odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);

	PHY_SetBBReg(adapt, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);



	/* One shot, path A LOK & IQK */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));

	ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);

	ODM_SetBBReg(dm_odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);

	PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);

	PHY_SetBBReg(adapt, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);



	/*  delay x ms */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));
@@ -636,7 +636,7 @@ phy_PathA_RxIQK(struct adapter *adapt, bool configPathB) 
	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xea4 = 0x%x\n", regEA4));



	/* reload RF 0xdf */

	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x00000000);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);

	ODM_SetRFReg(dm_odm, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);



	if (!(regeac & BIT27) &&		/* if Tx is OK, check whether Rx is OK */
@@ -660,8 +660,8 @@ phy_PathB_IQK_8188E(struct adapter *adapt) 


	/* One shot, path B LOK & IQK */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));

	ODM_SetBBReg(dm_odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002);

	ODM_SetBBReg(dm_odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000);

	PHY_SetBBReg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000002);

	PHY_SetBBReg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000000);



	/*  delay x ms */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,
@@ -724,9 +724,9 @@ static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u 
		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,

			     ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n",

			     X, TX0_A, Oldval_0));

		ODM_SetBBReg(dm_odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);

		PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);



		ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0>>7) & 0x1));

		PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(31), ((X * Oldval_0>>7) & 0x1));



		Y = result[final_candidate][1];

		if ((Y & 0x00000200) != 0)
@@ -734,10 +734,10 @@ static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u 


		TX0_C = (Y * Oldval_0) >> 8;

		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));

		ODM_SetBBReg(dm_odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));

		ODM_SetBBReg(dm_odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));

		PHY_SetBBReg(adapt, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));

		PHY_SetBBReg(adapt, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));



		ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0>>7) & 0x1));

		PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(29), ((Y * Oldval_0>>7) & 0x1));



		if (txonly) {

			ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("patha_fill_iqk only Tx OK\n"));
@@ -745,13 +745,13 @@ static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u 
		}



		reg = result[final_candidate][2];

		ODM_SetBBReg(dm_odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);

		PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0x3FF, reg);



		reg = result[final_candidate][3] & 0x3F;

		ODM_SetBBReg(dm_odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);

		PHY_SetBBReg(adapt, rOFDM0_XARxIQImbalance, 0xFC00, reg);



		reg = (result[final_candidate][3] >> 6) & 0xF;

		ODM_SetBBReg(dm_odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);

		PHY_SetBBReg(adapt, rOFDM0_RxIQExtAnta, 0xF0000000, reg);

	}

}
@@ -775,9 +775,9 @@ static void pathb_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u 
			X = X | 0xFFFFFC00;

		TX1_A = (X * Oldval_1) >> 8;

		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));

		ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);

		PHY_SetBBReg(adapt, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);



		ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1>>7) & 0x1));

		PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(27), ((X * Oldval_1>>7) & 0x1));



		Y = result[final_candidate][5];

		if ((Y & 0x00000200) != 0)
@@ -785,22 +785,22 @@ static void pathb_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8], u 


		TX1_C = (Y * Oldval_1) >> 8;

		ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));

		ODM_SetBBReg(dm_odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));

		ODM_SetBBReg(dm_odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));

		PHY_SetBBReg(adapt, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));

		PHY_SetBBReg(adapt, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));



		ODM_SetBBReg(dm_odm, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1>>7) & 0x1));

		PHY_SetBBReg(adapt, rOFDM0_ECCAThreshold, BIT(25), ((Y * Oldval_1>>7) & 0x1));



		if (txonly)

			return;



		reg = result[final_candidate][6];

		ODM_SetBBReg(dm_odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);

		PHY_SetBBReg(adapt, rOFDM0_XBRxIQImbalance, 0x3FF, reg);



		reg = result[final_candidate][7] & 0x3F;

		ODM_SetBBReg(dm_odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);

		PHY_SetBBReg(adapt, rOFDM0_XBRxIQImbalance, 0xFC00, reg);



		reg = (result[final_candidate][7] >> 6) & 0xF;

		ODM_SetBBReg(dm_odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);

		PHY_SetBBReg(adapt, rOFDM0_AGCRSSITable, 0x0000F000, reg);

	}

}
@@ -852,7 +852,7 @@ static void reload_adda_reg(struct adapter *adapt, u32 *ADDAReg, u32 *ADDABackup 


	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));

	for (i = 0; i < RegiesterNum; i++)

		ODM_SetBBReg(dm_odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);

		PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, ADDABackup[i]);

}



static void
@@ -890,13 +890,13 @@ _PHY_PathADDAOn( 
	pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;

	if (!is2t) {

		pathOn = 0x0bdb25a0;

		ODM_SetBBReg(dm_odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);

		PHY_SetBBReg(adapt, ADDAReg[0], bMaskDWord, 0x0b1b25a0);

	} else {

		ODM_SetBBReg(dm_odm, ADDAReg[0], bMaskDWord, pathOn);

		PHY_SetBBReg(adapt, ADDAReg[0], bMaskDWord, pathOn);

	}



	for (i = 1; i < IQK_ADDA_REG_NUM; i++)

		ODM_SetBBReg(dm_odm, ADDAReg[i], bMaskDWord, pathOn);

		PHY_SetBBReg(adapt, ADDAReg[i], bMaskDWord, pathOn);

}



void
@@ -930,9 +930,9 @@ _PHY_PathAStandBy( 


	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path-A standby mode!\n"));



	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x0);

	ODM_SetBBReg(dm_odm, 0x840, bMaskDWord, 0x00010000);

	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x0);

	PHY_SetBBReg(adapt, 0x840, bMaskDWord, 0x00010000);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);

}



static void _PHY_PIModeSwitch(
@@ -947,8 +947,8 @@ static void _PHY_PIModeSwitch( 
	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));



	mode = PIMode ? 0x01000100 : 0x01000000;

	ODM_SetBBReg(dm_odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);

	ODM_SetBBReg(dm_odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);

	PHY_SetBBReg(adapt, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);

	PHY_SetBBReg(adapt, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);

}



static bool phy_SimularityCompare_8188E(
@@ -1105,19 +1105,19 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t, 
	}



	/* BB setting */

	ODM_SetBBReg(dm_odm, rFPGA0_RFMOD, BIT24, 0x00);

	ODM_SetBBReg(dm_odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);

	ODM_SetBBReg(dm_odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);

	ODM_SetBBReg(dm_odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);

	PHY_SetBBReg(adapt, rFPGA0_RFMOD, BIT24, 0x00);

	PHY_SetBBReg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);

	PHY_SetBBReg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);

	PHY_SetBBReg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);



	ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);

	ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);

	ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);

	ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);

	PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);

	PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);

	PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);

	PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);



	if (is2t) {

		ODM_SetBBReg(dm_odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);

		ODM_SetBBReg(dm_odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);

		PHY_SetBBReg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);

		PHY_SetBBReg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);

	}



	/* MAC settings */
@@ -1125,16 +1125,16 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t, 


	/* Page B init */

	/* AP or IQK */

	ODM_SetBBReg(dm_odm, rConfig_AntA, bMaskDWord, 0x0f600000);

	PHY_SetBBReg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000);



	if (is2t)

		ODM_SetBBReg(dm_odm, rConfig_AntB, bMaskDWord, 0x0f600000);

		PHY_SetBBReg(adapt, rConfig_AntB, bMaskDWord, 0x0f600000);



	/*  IQ calibration setting */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));

	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0x80800000);

	ODM_SetBBReg(dm_odm, rTx_IQK, bMaskDWord, 0x01007c00);

	ODM_SetBBReg(dm_odm, rRx_IQK, bMaskDWord, 0x81004800);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);

	PHY_SetBBReg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);

	PHY_SetBBReg(adapt, rRx_IQK, bMaskDWord, 0x81004800);



	for (i = 0; i < retryCount; i++) {

		PathAOK = phy_PathA_IQK_8188E(adapt, is2t);
@@ -1191,7 +1191,7 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t, 


	/* Back to BB mode, load original value */

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));

	ODM_SetBBReg(dm_odm, rFPGA0_IQK, bMaskDWord, 0);

	PHY_SetBBReg(adapt, rFPGA0_IQK, bMaskDWord, 0);



	if (t != 0) {

		if (!dm_odm->RFCalibrateInfo.bRfPiEnable) {
@@ -1208,13 +1208,13 @@ static void phy_IQCalibrate_8188E(struct adapter *adapt, s32 result[][8], u8 t, 
		reload_adda_reg(adapt, IQK_BB_REG_92C, dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);



		/*  Restore RX initial gain */

		ODM_SetBBReg(dm_odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);

		PHY_SetBBReg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);

		if (is2t)

			ODM_SetBBReg(dm_odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);

			PHY_SetBBReg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);



		/* load 0xe30 IQC default value */

		ODM_SetBBReg(dm_odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);

		ODM_SetBBReg(dm_odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);

		PHY_SetBBReg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);

		PHY_SetBBReg(adapt, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);

	}

	ODM_RT_TRACE(dm_odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n"));

}
@@ -1475,19 +1475,19 @@ static void phy_setrfpathswitch_8188e(struct adapter *adapt, bool main, bool is2 
		u8 u1btmp;

		u1btmp = ODM_Read1Byte(dm_odm, REG_LEDCFG2) | BIT7;

		ODM_Write1Byte(dm_odm, REG_LEDCFG2, u1btmp);

		ODM_SetBBReg(dm_odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);

		PHY_SetBBReg(adapt, rFPGA0_XAB_RFParameter, BIT13, 0x01);

	}



	if (is2t) {	/* 92C */

		if (main)

			ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1);	/* 92C_Path_A */

			PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1);	/* 92C_Path_A */

		else

			ODM_SetBBReg(dm_odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2);	/* BT */

			PHY_SetBBReg(adapt, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2);	/* BT */

	} else {			/* 88C */

		if (main)

			ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2);	/* Main */

			PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2);	/* Main */

		else

			ODM_SetBBReg(dm_odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1);	/* Aux */

			PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1);	/* Aux */

	}

}

drivers/staging/rtl8188eu/hal/odm.c

+101 −93

File changed.

Preview size limit exceeded, changes collapsed.

drivers/staging/rtl8188eu/hal/odm_RTL8188E.c

+71 −65

File changed.

Preview size limit exceeded, changes collapsed.

drivers/staging/rtl8188eu/hal/odm_RegConfig8188E.c

+6 −2
Original line number Diff line number Diff line
@@ -70,7 +70,9 @@ void odm_ConfigMAC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u8 Data) 


void odm_ConfigBB_AGC_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)

{

	ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);

	struct adapter *adapter = pDM_Odm->Adapter;



	PHY_SetBBReg(adapter, Addr, Bitmask, Data);

	/*  Add 1us delay between BB/RF register setting. */

	udelay(1);
@@ -104,6 +106,8 @@ void odm_ConfigBB_PHY_REG_PG_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, 


void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask, u32 Data)

{

	struct adapter *adapter = pDM_Odm->Adapter;



	if (Addr == 0xfe) {

		msleep(50);

	} else if (Addr == 0xfd) {
@@ -119,7 +123,7 @@ void odm_ConfigBB_PHY_8188E(struct odm_dm_struct *pDM_Odm, u32 Addr, u32 Bitmask 
	} else {

		if (Addr == 0xa24)

			pDM_Odm->RFCalibrateInfo.RegA24 = Data;

		ODM_SetBBReg(pDM_Odm, Addr, Bitmask, Data);

		PHY_SetBBReg(adapter, Addr, Bitmask, Data);



		/*  Add 1us delay between BB/RF register setting. */

		udelay(1);

drivers/staging/rtl8188eu/hal/odm_interface.c

+0 −6
Original line number Diff line number Diff line
@@ -69,12 +69,6 @@ u32 ODM_GetMACReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask) 
	return PHY_QueryBBReg(Adapter, RegAddr, BitMask);

}



void ODM_SetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask, u32 Data)

{

	struct adapter *Adapter = pDM_Odm->Adapter;

	PHY_SetBBReg(Adapter, RegAddr, BitMask, Data);

}



u32 ODM_GetBBReg(struct odm_dm_struct *pDM_Odm, u32 RegAddr, u32 BitMask)

{

	struct adapter *Adapter = pDM_Odm->Adapter;