Commit e6e39557 authored by Anton Bambura's avatar Anton Bambura Committed by Thierry Reding
Browse files

ARM: tegra: Enable video decoder on Tegra114 



Add Video Decoder Engine node to Tegra114 device-tree.

Signed-off-by: default avatarAnton Bambura <jenneron@protonmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent a28c1b4f

arch/arm/boot/dts/tegra114.dtsi

+37 −0
Original line number Diff line number Diff line
@@ -17,6 +17,19 @@ memory@80000000 { 
		reg = <0x80000000 0x0>;

	};



	sram@40000000 {

		compatible = "mmio-sram";

		reg = <0x40000000 0x40000>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0 0x40000000 0x40000>;



		vde_pool: sram@400 {

			reg = <0x400 0x3fc00>;

			pool;

		};

	};



	host1x@50000000 {

		compatible = "nvidia,tegra114-host1x";

		reg = <0x50000000 0x00028000>;
@@ -253,6 +266,30 @@ gpio: gpio@6000d000 { 
		*/

	};



	vde@6001a000 {

		compatible = "nvidia,tegra114-vde";

		reg = <0x6001a000 0x1000>, /* Syntax Engine */

		      <0x6001b000 0x1000>, /* Video Bitstream Engine */

		      <0x6001c000  0x100>, /* Macroblock Engine */

		      <0x6001c200  0x100>, /* Post-processing Engine */

		      <0x6001c400  0x100>, /* Motion Compensation Engine */

		      <0x6001c600  0x100>, /* Transform Engine */

		      <0x6001c800  0x100>, /* Pixel prediction block */

		      <0x6001ca00  0x100>, /* Video DMA */

		      <0x6001d800  0x400>; /* Video frame controls */

		reg-names = "sxe", "bsev", "mbe", "ppe", "mce",

			    "tfe", "ppb", "vdma", "frameid";

		iram = <&vde_pool>; /* IRAM region */

		interrupts = <GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */

			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */

			     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */

		interrupt-names = "sync-token", "bsev", "sxe";

		clocks = <&tegra_car TEGRA114_CLK_VDE>;

		reset-names = "vde", "mc";

		resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>;

		iommus = <&mc TEGRA_SWGROUP_VDE>;

	};



	apbmisc@70000800 {

		compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc";

		reg = <0x70000800 0x64>, /* Chip revision */