Commit e7414a1a authored by Jake Wang's avatar Jake Wang Committed by Alex Deucher
Browse files

drm/amd/display: Disable hdmistream and hdmichar clocks 



[Why & How]
Disable hdmistream and hdmichar root clocks when not being used.

Reviewed-by: default avatarAric Cyr <Aric.Cyr@amd.com>
Acked-by: default avatarAgustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: default avatarJake Wang <haonan.wang2@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f2949a51

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h

+7 −2
Original line number Diff line number Diff line
@@ -186,8 +186,11 @@ 
	type SYMCLK32_ROOT_LE0_GATE_DISABLE;\

	type SYMCLK32_ROOT_LE1_GATE_DISABLE;\

	type DPSTREAMCLK_ROOT_GATE_DISABLE;\

	type DPSTREAMCLK_GATE_DISABLE;



	type DPSTREAMCLK_GATE_DISABLE;\

	type HDMISTREAMCLK0_DTO_PHASE;\

	type HDMISTREAMCLK0_DTO_MODULO;\

	type HDMICHARCLK0_GATE_DISABLE;\

	type HDMICHARCLK0_ROOT_GATE_DISABLE;





struct dccg_shift {
@@ -231,6 +234,8 @@ struct dccg_registers { 
	uint32_t DPSTREAMCLK_ROOT_GATE_DISABLE;

	uint32_t DPSTREAMCLK_GATE_DISABLE;

	uint32_t DCCG_GATE_DISABLE_CNTL3;

	uint32_t HDMISTREAMCLK0_DTO_PARAM;

	uint32_t DCCG_GATE_DISABLE_CNTL4;



};

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dccg.h

+5 −4
Original line number Diff line number Diff line
@@ -66,7 +66,8 @@ 
	SR(DSCCLK1_DTO_PARAM),\

	SR(DSCCLK2_DTO_PARAM),\

	SR(DSCCLK_DTO_CTRL),\

	SR(DCCG_GATE_DISABLE_CNTL3)

	SR(DCCG_GATE_DISABLE_CNTL3),\

	SR(HDMISTREAMCLK0_DTO_PARAM)





#define DCCG_MASK_SH_LIST_DCN31(mask_sh) \
@@ -141,9 +142,9 @@ 
	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE2_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_SE3_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE0_GATE_DISABLE, mask_sh),\

	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh)





	DCCG_SF(DCCG_GATE_DISABLE_CNTL3, SYMCLK32_ROOT_LE1_GATE_DISABLE, mask_sh),\

	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_PHASE, mask_sh),\

	DCCG_SF(HDMISTREAMCLK0_DTO_PARAM, HDMISTREAMCLK0_DTO_MODULO, mask_sh)





struct dccg *dccg31_create(

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_offset.h

+2 −0
Original line number Diff line number Diff line
@@ -436,6 +436,8 @@ 
#define regPHYESYMCLK_CLOCK_CNTL_BASE_IDX                                                               2

#define regDCCG_GATE_DISABLE_CNTL3                                                                      0x005a

#define regDCCG_GATE_DISABLE_CNTL3_BASE_IDX                                                             2

#define regHDMISTREAMCLK0_DTO_PARAM                                                                     0x005b

#define regHDMISTREAMCLK0_DTO_PARAM_BASE_IDX                                                            2

#define regDCCG_AUDIO_DTBCLK_DTO_PHASE                                                                  0x0061

#define regDCCG_AUDIO_DTBCLK_DTO_PHASE_BASE_IDX                                                         2

#define regDCCG_AUDIO_DTBCLK_DTO_MODULO                                                                 0x0062

drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_2_sh_mask.h

+8 −0
Original line number Diff line number Diff line
@@ -1438,6 +1438,14 @@ 
#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE0_GATE_DISABLE_MASK                                               0x00200000L

#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_LE1_GATE_DISABLE_MASK                                          0x00400000L

#define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_LE1_GATE_DISABLE_MASK                                               0x00800000L

//HDMISTREAMCLK0_DTO_PARAM

#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE__SHIFT                                             0x0

#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO__SHIFT                                            0x8

#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN__SHIFT                                                0x10

#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_PHASE_MASK                                               0x000000FFL

#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_MODULO_MASK                                              0x0000FF00L

#define HDMISTREAMCLK0_DTO_PARAM__HDMISTREAMCLK0_DTO_EN_MASK                                                  0x00010000L









//DCCG_AUDIO_DTBCLK_DTO_PHASE









#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE__SHIFT                                       0x0









#define DCCG_AUDIO_DTBCLK_DTO_PHASE__DCCG_AUDIO_DTBCLK_DTO_PHASE_MASK                                         0xFFFFFFFFL