Commit e7bae9bb authored by Jonathan Cameron's avatar Jonathan Cameron
Browse files

dt-bindings:iio:resolver:adi,ad2s90: Conversion of binding to yaml. 



Simple binding with a good description of why the spi-max-frequency is,
in practice not as high as the datasheet implies.  I've set the
maximum as per the value established in the description.

Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Cc: Matheus Tavares <matheus.bernardino@usp.br>
Cc: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201031184854.745828-2-jic23@kernel.org
parent 74d826da

Documentation/devicetree/bindings/iio/resolver/ad2s90.txt

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Analog Devices AD2S90 Resolver-to-Digital Converter



https://www.analog.com/en/products/ad2s90.html



Required properties:

  - compatible: should be "adi,ad2s90"

  - reg: SPI chip select number for the device

  - spi-max-frequency: set maximum clock frequency, must be 830000

  - spi-cpol and spi-cpha:

        Either SPI mode (0,0) or (1,1) must be used, so specify none or both of

        spi-cpha, spi-cpol.



See for more details:

    Documentation/devicetree/bindings/spi/spi-bus.txt



Note about max frequency:

    Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns

    delay is expected between the application of a logic LO to CS and the

    application of SCLK, as also specified. And since the delay is not

    implemented in the spi code, to satisfy it, SCLK's period should be at most

    2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives

    roughly 830000Hz.



Example:

resolver@0 {

	compatible = "adi,ad2s90";

	reg = <0>;

	spi-max-frequency = <830000>;

	spi-cpol;

	spi-cpha;

};

Documentation/devicetree/bindings/iio/resolver/adi,ad2s90.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/iio/resolver/adi,ad2s90.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Analog Devices AD2S90 Resolver-to-Digital Converter



maintainers:

  - Matheus Tavares <matheus.bernardino@usp.br>



description: |

  Datasheet: https://www.analog.com/en/products/ad2s90.html



properties:

  compatible:

    const: adi,ad2s90



  reg:

    maxItems: 1



  spi-max-frequency:

    maximum: 830000

    description: |

      Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns

      delay is expected between the application of a logic LO to CS and the

      application of SCLK, as also specified. And since the delay is not

      implemented in the spi code, to satisfy it, SCLK's period should be at

      most 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives

      roughly 830000Hz.



  spi-cpol: true



  spi-cpha: true



additionalProperties: false



required:

  - compatible

  - reg



dependencies:

  spi-cpol: [ spi-cpha ]

  spi-cpha: [ spi-cpol ]



examples:

  - |

    spi {

        #address-cells = <1>;

        #size-cells = <0>;



        resolver@0 {

            compatible = "adi,ad2s90";

            reg = <0>;

            spi-max-frequency = <830000>;

            spi-cpol;

            spi-cpha;

        };

    };

...