net: mvpp2: introduce PPv2.2 HW descriptors and adapt accessors (e7c5359f) · Commits · jan.koester / Linux

drivers/net/ethernet/marvell/mvpp2.c

+76 −12

Original line number	Original line	Diff line number	Diff line
	@@ -767,18 +767,42 @@ struct mvpp21_rx_desc {
	u32 reserved8;		u32 reserved8;
	};		};

			/* HW TX descriptor for PPv2.2 */
			struct mvpp22_tx_desc {
			u32 command;
			u8 packet_offset;
			u8 phys_txq;
			u16 data_size;
			u64 reserved1;
			u64 buf_dma_addr_ptp;
			u64 buf_cookie_misc;
			};

			/* HW RX descriptor for PPv2.2 */
			struct mvpp22_rx_desc {
			u32 status;
			u16 reserved1;
			u16 data_size;
			u32 reserved2;
			u32 reserved3;
			u64 buf_dma_addr_key_hash;
			u64 buf_cookie_misc;
			};

	/* Opaque type used by the driver to manipulate the HW TX and RX		/* Opaque type used by the driver to manipulate the HW TX and RX
	* descriptors		* descriptors
	*/		*/
	struct mvpp2_tx_desc {		struct mvpp2_tx_desc {
	union {		union {
	struct mvpp21_tx_desc pp21;		struct mvpp21_tx_desc pp21;
			struct mvpp22_tx_desc pp22;
	};		};
	};		};

	struct mvpp2_rx_desc {		struct mvpp2_rx_desc {
	union {		union {
	struct mvpp21_rx_desc pp21;		struct mvpp21_rx_desc pp21;
			struct mvpp22_rx_desc pp22;
	};		};
	};		};

	@@ -969,78 +993,118 @@ static u32 mvpp2_read(struct mvpp2 *priv, u32 offset)
	static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,		static dma_addr_t mvpp2_txdesc_dma_addr_get(struct mvpp2_port *port,
	struct mvpp2_tx_desc *tx_desc)		struct mvpp2_tx_desc *tx_desc)
	{		{
			if (port->priv->hw_version == MVPP21)
	return tx_desc->pp21.buf_dma_addr;		return tx_desc->pp21.buf_dma_addr;
			else
			return tx_desc->pp22.buf_dma_addr_ptp & GENMASK_ULL(40, 0);
	}		}

	static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,		static void mvpp2_txdesc_dma_addr_set(struct mvpp2_port *port,
	struct mvpp2_tx_desc *tx_desc,		struct mvpp2_tx_desc *tx_desc,
	dma_addr_t dma_addr)		dma_addr_t dma_addr)
	{		{
			if (port->priv->hw_version == MVPP21) {
	tx_desc->pp21.buf_dma_addr = dma_addr;		tx_desc->pp21.buf_dma_addr = dma_addr;
			} else {
			u64 val = (u64)dma_addr;

			tx_desc->pp22.buf_dma_addr_ptp &= ~GENMASK_ULL(40, 0);
			tx_desc->pp22.buf_dma_addr_ptp \|= val;
			}
	}		}

	static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,		static size_t mvpp2_txdesc_size_get(struct mvpp2_port *port,
	struct mvpp2_tx_desc *tx_desc)		struct mvpp2_tx_desc *tx_desc)
	{		{
			if (port->priv->hw_version == MVPP21)
	return tx_desc->pp21.data_size;		return tx_desc->pp21.data_size;
			else
			return tx_desc->pp22.data_size;
	}		}

	static void mvpp2_txdesc_size_set(struct mvpp2_port *port,		static void mvpp2_txdesc_size_set(struct mvpp2_port *port,
	struct mvpp2_tx_desc *tx_desc,		struct mvpp2_tx_desc *tx_desc,
	size_t size)		size_t size)
	{		{
			if (port->priv->hw_version == MVPP21)
	tx_desc->pp21.data_size = size;		tx_desc->pp21.data_size = size;
			else
			tx_desc->pp22.data_size = size;
	}		}

	static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,		static void mvpp2_txdesc_txq_set(struct mvpp2_port *port,
	struct mvpp2_tx_desc *tx_desc,		struct mvpp2_tx_desc *tx_desc,
	unsigned int txq)		unsigned int txq)
	{		{
			if (port->priv->hw_version == MVPP21)
	tx_desc->pp21.phys_txq = txq;		tx_desc->pp21.phys_txq = txq;
			else
			tx_desc->pp22.phys_txq = txq;
	}		}

	static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,		static void mvpp2_txdesc_cmd_set(struct mvpp2_port *port,
	struct mvpp2_tx_desc *tx_desc,		struct mvpp2_tx_desc *tx_desc,
	unsigned int command)		unsigned int command)
	{		{
			if (port->priv->hw_version == MVPP21)
	tx_desc->pp21.command = command;		tx_desc->pp21.command = command;
			else
			tx_desc->pp22.command = command;
	}		}

	static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,		static void mvpp2_txdesc_offset_set(struct mvpp2_port *port,
	struct mvpp2_tx_desc *tx_desc,		struct mvpp2_tx_desc *tx_desc,
	unsigned int offset)		unsigned int offset)
	{		{
			if (port->priv->hw_version == MVPP21)
	tx_desc->pp21.packet_offset = offset;		tx_desc->pp21.packet_offset = offset;
			else
			tx_desc->pp22.packet_offset = offset;
	}		}

	static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,		static unsigned int mvpp2_txdesc_offset_get(struct mvpp2_port *port,
	struct mvpp2_tx_desc *tx_desc)		struct mvpp2_tx_desc *tx_desc)
	{		{
			if (port->priv->hw_version == MVPP21)
	return tx_desc->pp21.packet_offset;		return tx_desc->pp21.packet_offset;
			else
			return tx_desc->pp22.packet_offset;
	}		}

	static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,		static dma_addr_t mvpp2_rxdesc_dma_addr_get(struct mvpp2_port *port,
	struct mvpp2_rx_desc *rx_desc)		struct mvpp2_rx_desc *rx_desc)
	{		{
			if (port->priv->hw_version == MVPP21)
	return rx_desc->pp21.buf_dma_addr;		return rx_desc->pp21.buf_dma_addr;
			else
			return rx_desc->pp22.buf_dma_addr_key_hash & GENMASK_ULL(40, 0);
	}		}

	static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,		static unsigned long mvpp2_rxdesc_cookie_get(struct mvpp2_port *port,
	struct mvpp2_rx_desc *rx_desc)		struct mvpp2_rx_desc *rx_desc)
	{		{
			if (port->priv->hw_version == MVPP21)
	return rx_desc->pp21.buf_cookie;		return rx_desc->pp21.buf_cookie;
			else
			return rx_desc->pp22.buf_cookie_misc & GENMASK_ULL(40, 0);
	}		}

	static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,		static size_t mvpp2_rxdesc_size_get(struct mvpp2_port *port,
	struct mvpp2_rx_desc *rx_desc)		struct mvpp2_rx_desc *rx_desc)
	{		{
			if (port->priv->hw_version == MVPP21)
	return rx_desc->pp21.data_size;		return rx_desc->pp21.data_size;
			else
			return rx_desc->pp22.data_size;
	}		}

	static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,		static u32 mvpp2_rxdesc_status_get(struct mvpp2_port *port,
	struct mvpp2_rx_desc *rx_desc)		struct mvpp2_rx_desc *rx_desc)
	{		{
			if (port->priv->hw_version == MVPP21)
	return rx_desc->pp21.status;		return rx_desc->pp21.status;
			else
			return rx_desc->pp22.status;
	}		}

	static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)		static void mvpp2_txq_inc_get(struct mvpp2_txq_pcpu *txq_pcpu)