Commit e8e095b3 authored by Sunil Goutham's avatar Sunil Goutham Committed by David S. Miller
Browse files

octeontx2-af: cn10k: Bandwidth profiles config support 



CN10K silicons supports hierarchial ingress packet ratelimiting.
There are 3 levels of profilers supported leaf, mid and top.
Ratelimiting is done after packet forwarding decision is taken
and a NIXLF's RQ is identified to DMA the packet. RQ's context
points to a leaf bandwidth profile which can be configured
to achieve desired ratelimit.

This patch adds logic for management of these bandwidth profiles
ie profile alloc, free, context update etc.

Signed-off-by: default avatarSunil Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarSubbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ad5645d7

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+39 −1
Original line number Diff line number Diff line
@@ -260,7 +260,11 @@ M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \ 
M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \

M(NIX_CN10K_AQ_ENQ,	0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \

				nix_cn10k_aq_enq_rsp)			\

M(NIX_GET_HW_INFO,	0x801a, nix_get_hw_info, msg_req, nix_hw_info)

M(NIX_GET_HW_INFO,	0x801c, nix_get_hw_info, msg_req, nix_hw_info)	\

M(NIX_BANDPROF_ALLOC,	0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \

				nix_bandprof_alloc_rsp)			    \

M(NIX_BANDPROF_FREE,	0x801e, nix_bandprof_free, nix_bandprof_free_req,   \

				msg_rsp)



/* Messages initiated by AF (range 0xC00 - 0xDFF) */

#define MBOX_UP_CGX_MESSAGES						\
@@ -615,6 +619,9 @@ enum nix_af_status { 
	NIX_AF_ERR_PTP_CONFIG_FAIL  = -423,

	NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,

	NIX_AF_ERR_INVALID_NIXBLK   = -425,

	NIX_AF_ERR_INVALID_BANDPROF = -426,

	NIX_AF_ERR_IPOLICER_NOTSUPP = -427,

	NIX_AF_ERR_BANDPROF_INVAL_REQ  = -428,

};



/* For NIX RX vtag action  */
@@ -683,6 +690,7 @@ struct nix_cn10k_aq_enq_req { 
		struct nix_cq_ctx_s cq;

		struct nix_rsse_s   rss;

		struct nix_rx_mce_s mce;

		struct nix_bandprof_s prof;

	};

	union {

		struct nix_cn10k_rq_ctx_s rq_mask;
@@ -690,6 +698,7 @@ struct nix_cn10k_aq_enq_req { 
		struct nix_cq_ctx_s cq_mask;

		struct nix_rsse_s   rss_mask;

		struct nix_rx_mce_s mce_mask;

		struct nix_bandprof_s prof_mask;

	};

};
@@ -701,6 +710,7 @@ struct nix_cn10k_aq_enq_rsp { 
		struct nix_cq_ctx_s cq;

		struct nix_rsse_s   rss;

		struct nix_rx_mce_s mce;

		struct nix_bandprof_s prof;

	};

};
@@ -716,6 +726,7 @@ struct nix_aq_enq_req { 
		struct nix_cq_ctx_s cq;

		struct nix_rsse_s   rss;

		struct nix_rx_mce_s mce;

		u64 prof;

	};

	union {

		struct nix_rq_ctx_s rq_mask;
@@ -723,6 +734,7 @@ struct nix_aq_enq_req { 
		struct nix_cq_ctx_s cq_mask;

		struct nix_rsse_s   rss_mask;

		struct nix_rx_mce_s mce_mask;

		u64 prof_mask;

	};

};
@@ -734,6 +746,7 @@ struct nix_aq_enq_rsp { 
		struct nix_cq_ctx_s cq;

		struct nix_rsse_s   rss;

		struct nix_rx_mce_s mce;

		u64 prof;

	};

};
@@ -975,6 +988,31 @@ struct nix_hw_info { 
	u16 min_mtu;

};



struct nix_bandprof_alloc_req {

	struct mbox_msghdr hdr;

	/* Count of profiles needed per layer */

	u16 prof_count[BAND_PROF_NUM_LAYERS];

};



struct nix_bandprof_alloc_rsp {

	struct mbox_msghdr hdr;

	u16 prof_count[BAND_PROF_NUM_LAYERS];



	/* There is no need to allocate morethan 1 bandwidth profile

	 * per RQ of a PF_FUNC's NIXLF. So limit the maximum

	 * profiles to 64 per PF_FUNC.

	 */

#define MAX_BANDPROF_PER_PFFUNC	64

	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];

};



struct nix_bandprof_free_req {

	struct mbox_msghdr hdr;

	u8 free_all;

	u16 prof_count[BAND_PROF_NUM_LAYERS];

	u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];

};



/* NPC mbox message structs */



#define NPC_MCAM_ENTRY_INVALID	0xFFFF

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

+11 −0
Original line number Diff line number Diff line
@@ -296,6 +296,13 @@ struct nix_txvlan { 
	struct mutex rsrc_lock; /* Serialize resource alloc/free */

};



struct nix_ipolicer {

	struct rsrc_bmap band_prof;

	u16 *pfvf_map;

	u16 *match_id;

	u16 *ref_count;

};



struct nix_hw {

	int blkaddr;

	struct rvu *rvu;
@@ -305,6 +312,7 @@ struct nix_hw { 
	struct nix_mark_format mark_format;

	struct nix_lso lso;

	struct nix_txvlan txvlan;

	struct nix_ipolicer *ipolicer;

};



/* RVU block's capabilities or functionality,
@@ -322,6 +330,7 @@ struct hw_cap { 
	bool	nix_rx_multicast;	 /* Rx packet replication support */

	bool	per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */

	bool	programmable_chans; /* Channels programmable ? */

	bool	ipolicer;

};



struct rvu_hwinfo {
@@ -672,6 +681,8 @@ int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr); 
void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);

int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,

			struct nix_hw **nix_hw, int *blkaddr);

int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,

				 u16 rq_idx, u16 match_id);



/* NPC APIs */

int rvu_npc_init(struct rvu *rvu);

drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c

+617 −2

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c

+5 −0
Original line number Diff line number Diff line
@@ -1110,6 +1110,11 @@ static int npc_install_flow(struct rvu *rvu, int blkaddr, u16 target, 
	    req->vtag0_type == NIX_AF_LFX_RX_VTAG_TYPE7)

		rule->vfvlan_cfg = true;



	if (is_npc_intf_rx(req->intf) && req->match_id &&

	    (req->op == NIX_RX_ACTIONOP_UCAST || req->op == NIX_RX_ACTIONOP_RSS))

		return rvu_nix_setup_ratelimit_aggr(rvu, req->hdr.pcifunc,

					     req->index, req->match_id);



	return 0;

}

drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h

+8 −0
Original line number Diff line number Diff line
@@ -171,6 +171,7 @@ 
#define NIX_AF_SQ_CONST			(0x0040)

#define NIX_AF_CQ_CONST			(0x0048)

#define NIX_AF_RQ_CONST			(0x0050)

#define NIX_AF_PL_CONST			(0x0058)

#define NIX_AF_PSE_CONST		(0x0060)

#define NIX_AF_TL1_CONST		(0x0070)

#define NIX_AF_TL2_CONST		(0x0078)
@@ -181,6 +182,7 @@ 
#define NIX_AF_LSO_CFG			(0x00A8)

#define NIX_AF_BLK_RST			(0x00B0)

#define NIX_AF_TX_TSTMP_CFG		(0x00C0)

#define NIX_AF_PL_TS			(0x00C8)

#define NIX_AF_RX_CFG			(0x00D0)

#define NIX_AF_AVG_DELAY		(0x00E0)

#define NIX_AF_CINT_DELAY		(0x00F0)
@@ -212,7 +214,9 @@ 
#define NIX_AF_RX_DEF_OL2		(0x0200)

#define NIX_AF_RX_DEF_OIP4		(0x0210)

#define NIX_AF_RX_DEF_IIP4		(0x0220)

#define NIX_AF_RX_DEF_VLAN0_PCP_DEI	(0x0228)

#define NIX_AF_RX_DEF_OIP6		(0x0230)

#define NIX_AF_RX_DEF_VLAN1_PCP_DEI	(0x0238)

#define NIX_AF_RX_DEF_IIP6		(0x0240)

#define NIX_AF_RX_DEF_OTCP		(0x0250)

#define NIX_AF_RX_DEF_ITCP		(0x0260)
@@ -223,6 +227,10 @@ 
#define NIX_AF_RX_DEF_ISCTP		(0x02A0)

#define NIX_AF_RX_DEF_IPSECX		(0x02B0)

#define NIX_AF_RX_DEF_CST_APAD1		(0x02A8)

#define NIX_AF_RX_DEF_IIP4_DSCP		(0x02E0)

#define NIX_AF_RX_DEF_OIP4_DSCP		(0x02E8)

#define NIX_AF_RX_DEF_IIP6_DSCP		(0x02F0)

#define NIX_AF_RX_DEF_OIP6_DSCP		(0x02F8)

#define NIX_AF_RX_IPSEC_GEN_CFG		(0x0300)

#define NIX_AF_RX_CPTX_INST_ADDR	(0x0310)

#define NIX_AF_NDC_TX_SYNC		(0x03F0)