Commit e922057b authored by Jake Wang's avatar Jake Wang Committed by Alex Deucher
Browse files

drm/amd/display: Added support for multiple eDP BL control 



[WHY & HOW]
Driver currently assumes only 1 eDP is connected. Added support for
multiple eDP BL control.

Signed-off-by: default avatarJake Wang <haonan.wang2@amd.com>
Acked-by: default avatarBindu Ramamurthy <bindur12@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 86c8236e

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c

+2 −0
Original line number Diff line number Diff line
@@ -218,6 +218,8 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, 
	cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;

	cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = frame_ramp;

	cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_pwm_u16_16;

	cmd.abm_set_backlight.abm_set_backlight_data.version = DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1;

	cmd.abm_set_backlight.abm_set_backlight_data.panel_mask = (0x01 << panel_cntl->inst);

	cmd.abm_set_backlight.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_backlight_data);



	dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd);

drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h

+27 −0
Original line number Diff line number Diff line
@@ -120,6 +120,16 @@ 
/* Trace buffer offset for entry */

#define TRACE_BUFFER_ENTRY_OFFSET  16



/**

 * ABM backlight control version legacy

 */

#define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_UNKNOWN 0x0



/**

 * ABM backlight control version with multi edp support

 */

#define DMUB_CMD_ABM_SET_BACKLIGHT_VERSION_1 0x1



/**

 * Physical framebuffer address location, 64-bit.

 */
@@ -1625,6 +1635,23 @@ struct dmub_cmd_abm_set_backlight_data { 
	 * Requested backlight level from user.

	 */

	uint32_t backlight_user_level;



	/**

	 * Backlight data version.

	 */

	uint8_t version;



	/**

	 * Panel Control HW instance mask.

	 * Bit 0 is Panel Control HW instance 0.

	 * Bit 1 is Panel Control HW instance 1.

	 */

	uint8_t panel_mask;



	/**

	 * Explicit padding to 4 byte boundary.

	 */

	uint8_t pad[2];

};



/**