Commit e98dd3db authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Linus Walleij
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pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file 



Move all related code for SoC MT7621 into a new driver located
in 'pinctrl-mt7621.c' source file.

Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Link: https://lore.kernel.org/r/20210604115159.8834-3-sergio.paracuellos@gmail.com


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 276e552e

arch/mips/ralink/mt7621.c

+0 −88
Original line number Diff line number Diff line
@@ -18,97 +18,10 @@ 
#include <asm/mach-ralink/ralink_regs.h>

#include <asm/mach-ralink/mt7621.h>



#include <pinmux.h>



#include "common.h"



#define MT7621_GPIO_MODE_UART1		1

#define MT7621_GPIO_MODE_I2C		2

#define MT7621_GPIO_MODE_UART3_MASK	0x3

#define MT7621_GPIO_MODE_UART3_SHIFT	3

#define MT7621_GPIO_MODE_UART3_GPIO	1

#define MT7621_GPIO_MODE_UART2_MASK	0x3

#define MT7621_GPIO_MODE_UART2_SHIFT	5

#define MT7621_GPIO_MODE_UART2_GPIO	1

#define MT7621_GPIO_MODE_JTAG		7

#define MT7621_GPIO_MODE_WDT_MASK	0x3

#define MT7621_GPIO_MODE_WDT_SHIFT	8

#define MT7621_GPIO_MODE_WDT_GPIO	1

#define MT7621_GPIO_MODE_PCIE_RST	0

#define MT7621_GPIO_MODE_PCIE_REF	2

#define MT7621_GPIO_MODE_PCIE_MASK	0x3

#define MT7621_GPIO_MODE_PCIE_SHIFT	10

#define MT7621_GPIO_MODE_PCIE_GPIO	1

#define MT7621_GPIO_MODE_MDIO_MASK	0x3

#define MT7621_GPIO_MODE_MDIO_SHIFT	12

#define MT7621_GPIO_MODE_MDIO_GPIO	1

#define MT7621_GPIO_MODE_RGMII1		14

#define MT7621_GPIO_MODE_RGMII2		15

#define MT7621_GPIO_MODE_SPI_MASK	0x3

#define MT7621_GPIO_MODE_SPI_SHIFT	16

#define MT7621_GPIO_MODE_SPI_GPIO	1

#define MT7621_GPIO_MODE_SDHCI_MASK	0x3

#define MT7621_GPIO_MODE_SDHCI_SHIFT	18

#define MT7621_GPIO_MODE_SDHCI_GPIO	1



static void *detect_magic __initdata = detect_memory_region;



static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };

static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };

static struct rt2880_pmx_func uart3_grp[] = {

	FUNC("uart3", 0, 5, 4),

	FUNC("i2s", 2, 5, 4),

	FUNC("spdif3", 3, 5, 4),

};

static struct rt2880_pmx_func uart2_grp[] = {

	FUNC("uart2", 0, 9, 4),

	FUNC("pcm", 2, 9, 4),

	FUNC("spdif2", 3, 9, 4),

};

static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };

static struct rt2880_pmx_func wdt_grp[] = {

	FUNC("wdt rst", 0, 18, 1),

	FUNC("wdt refclk", 2, 18, 1),

};

static struct rt2880_pmx_func pcie_rst_grp[] = {

	FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),

	FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)

};

static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };

static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };

static struct rt2880_pmx_func spi_grp[] = {

	FUNC("spi", 0, 34, 7),

	FUNC("nand1", 2, 34, 7),

};

static struct rt2880_pmx_func sdhci_grp[] = {

	FUNC("sdhci", 0, 41, 8),

	FUNC("nand2", 2, 41, 8),

};

static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };



static struct rt2880_pmx_group mt7621_pinmux_data[] = {

	GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),

	GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),

	GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,

		MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),

	GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,

		MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),

	GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),

	GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,

		MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),

	GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,

		MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),

	GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,

		MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),

	GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),

	GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,

		MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),

	GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,

		MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),

	GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),

	{ 0 }

};



phys_addr_t mips_cpc_default_phys_base(void)

{

	panic("Cannot detect cpc address");
@@ -219,7 +132,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) 
		(rev & CHIP_REV_ECO_MASK));



	soc_info->mem_detect = mt7621_memory_detect;

	rt2880_pinmux_data = mt7621_pinmux_data;



	soc_dev_init(soc_info, rev);

drivers/pinctrl/ralink/Kconfig

+5 −0
Original line number Diff line number Diff line
@@ -11,4 +11,9 @@ config PINCTRL_RT2880 
        select PINMUX

        select GENERIC_PINCONF



config PINCTRL_MT7621

        bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs"

        depends on RALINK && SOC_MT7621

        select PINCTRL_RT2880



endmenu

drivers/pinctrl/ralink/Makefile

+2 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

obj-$(CONFIG_PINCTRL_RT2880)   += pinctrl-rt2880.o



obj-$(CONFIG_PINCTRL_MT7621)   += pinctrl-mt7621.o

drivers/pinctrl/ralink/pinctrl-mt7621.c

0 → 100644
+116 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only



#include <linux/module.h>

#include <linux/platform_device.h>

#include <linux/of.h>

#include "pinmux.h"



#define MT7621_GPIO_MODE_UART1		1

#define MT7621_GPIO_MODE_I2C		2

#define MT7621_GPIO_MODE_UART3_MASK	0x3

#define MT7621_GPIO_MODE_UART3_SHIFT	3

#define MT7621_GPIO_MODE_UART3_GPIO	1

#define MT7621_GPIO_MODE_UART2_MASK	0x3

#define MT7621_GPIO_MODE_UART2_SHIFT	5

#define MT7621_GPIO_MODE_UART2_GPIO	1

#define MT7621_GPIO_MODE_JTAG		7

#define MT7621_GPIO_MODE_WDT_MASK	0x3

#define MT7621_GPIO_MODE_WDT_SHIFT	8

#define MT7621_GPIO_MODE_WDT_GPIO	1

#define MT7621_GPIO_MODE_PCIE_RST	0

#define MT7621_GPIO_MODE_PCIE_REF	2

#define MT7621_GPIO_MODE_PCIE_MASK	0x3

#define MT7621_GPIO_MODE_PCIE_SHIFT	10

#define MT7621_GPIO_MODE_PCIE_GPIO	1

#define MT7621_GPIO_MODE_MDIO_MASK	0x3

#define MT7621_GPIO_MODE_MDIO_SHIFT	12

#define MT7621_GPIO_MODE_MDIO_GPIO	1

#define MT7621_GPIO_MODE_RGMII1		14

#define MT7621_GPIO_MODE_RGMII2		15

#define MT7621_GPIO_MODE_SPI_MASK	0x3

#define MT7621_GPIO_MODE_SPI_SHIFT	16

#define MT7621_GPIO_MODE_SPI_GPIO	1

#define MT7621_GPIO_MODE_SDHCI_MASK	0x3

#define MT7621_GPIO_MODE_SDHCI_SHIFT	18

#define MT7621_GPIO_MODE_SDHCI_GPIO	1



static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };

static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };

static struct rt2880_pmx_func uart3_grp[] = {

	FUNC("uart3", 0, 5, 4),

	FUNC("i2s", 2, 5, 4),

	FUNC("spdif3", 3, 5, 4),

};

static struct rt2880_pmx_func uart2_grp[] = {

	FUNC("uart2", 0, 9, 4),

	FUNC("pcm", 2, 9, 4),

	FUNC("spdif2", 3, 9, 4),

};

static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };

static struct rt2880_pmx_func wdt_grp[] = {

	FUNC("wdt rst", 0, 18, 1),

	FUNC("wdt refclk", 2, 18, 1),

};

static struct rt2880_pmx_func pcie_rst_grp[] = {

	FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1),

	FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1)

};

static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) };

static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) };

static struct rt2880_pmx_func spi_grp[] = {

	FUNC("spi", 0, 34, 7),

	FUNC("nand1", 2, 34, 7),

};

static struct rt2880_pmx_func sdhci_grp[] = {

	FUNC("sdhci", 0, 41, 8),

	FUNC("nand2", 2, 41, 8),

};

static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) };



static struct rt2880_pmx_group mt7621_pinmux_data[] = {

	GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),

	GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),

	GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK,

		MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT),

	GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK,

		MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT),

	GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),

	GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,

		MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),

	GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK,

		MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT),

	GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK,

		MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT),

	GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2),

	GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK,

		MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT),

	GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,

		MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT),

	GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1),

	{ 0 }

};



static int mt7621_pinmux_probe(struct platform_device *pdev)

{

	return rt2880_pinmux_init(pdev, mt7621_pinmux_data);

}



static const struct of_device_id mt7621_pinmux_match[] = {

	{ .compatible = "ralink,rt2880-pinmux" },

	{}

};

MODULE_DEVICE_TABLE(of, mt7621_pinmux_match);



static struct platform_driver mt7621_pinmux_driver = {

	.probe = mt7621_pinmux_probe,

	.driver = {

		.name = "rt2880-pinmux",

		.of_match_table = mt7621_pinmux_match,

	},

};



static int __init mt7621_pinmux_init(void)

{

	return platform_driver_register(&mt7621_pinmux_driver);

}

core_initcall_sync(mt7621_pinmux_init);