Commit ebc7de22 authored by Oliver Endriss's avatar Oliver Endriss Committed by Mauro Carvalho Chehab
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[media] DRX-K: Tons of coding-style fixes 



Tons of coding-style fixes

Signed-off-by: default avatarOliver Endriss <o.endriss@gmx.de>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 874f6518

drivers/media/dvb/frontends/drxk_hard.c

+2330 −2012

File changed.

Preview size limit exceeded, changes collapsed.

drivers/media/dvb/frontends/drxk_hard.h

+114 −117
Original line number Diff line number Diff line
@@ -52,7 +52,7 @@ enum OperationMode { 
	OM_DVBT

};



typedef enum {

enum DRXPowerMode {

	DRX_POWER_UP = 0,

	DRX_POWER_MODE_1,

	DRX_POWER_MODE_2,
@@ -72,7 +72,7 @@ typedef enum { 
	DRX_POWER_MODE_15,

	DRX_POWER_MODE_16,

	DRX_POWER_DOWN = 255

}DRXPowerMode_t, *pDRXPowerMode_t;

};





/** /brief Intermediate power mode for DRXK, power down OFDM clock domain */
@@ -164,8 +164,7 @@ struct DRXKCfgDvbtEchoThres_t { 
	enum DRXFftmode_t      fftMode;

} ;



struct SCfgAgc

{

struct SCfgAgc {

	enum AGC_CTRL_MODE     ctrlMode;        /* off, user, auto */

	u16            outputLevel;     /* range dependent on AGC */

	u16            minOutputLevel;  /* range dependent on AGC */
@@ -178,14 +177,12 @@ struct SCfgAgc 
	u16            FastClipCtrlDelay;

};



struct SCfgPreSaw

{

struct SCfgPreSaw {

	u16        reference; /* pre SAW reference value, range 0 .. 31 */

	bool          usePreSaw; /* TRUE algorithms must use pre SAW sense */

};



struct DRXKOfdmScCmd_t

{

struct DRXKOfdmScCmd_t {

	u16 cmd;        /**< Command number */

	u16 subcmd;     /**< Sub-command parameter*/

	u16 param0;     /**< General purpous param */
@@ -208,7 +205,7 @@ struct drxk_state { 
	struct mutex mutex;

	struct mutex ctlock;



	u32           m_Instance;             ///< Channel 1,2,3 or 4

	u32    m_Instance;           /**< Channel 1,2,3 or 4 */



	int    m_ChunkSize;

	u8 Chunk[256];
@@ -229,22 +226,22 @@ struct drxk_state { 
	u16    m_HICfgWakeUpKey;

	u16    m_HICfgTimeout;

	u16    m_HICfgCtrl;

	s32            m_sysClockFreq     ;    ///< system clock frequency in kHz



	enum EDrxkState      m_DrxkState;            ///< State of Drxk (init,stopped,started)

	enum OperationMode   m_OperationMode;        ///< digital standards

	struct SCfgAgc         m_vsbRfAgcCfg;          ///< settings for VSB RF-AGC

	struct SCfgAgc         m_vsbIfAgcCfg;          ///< settings for VSB IF-AGC

	u16          m_vsbPgaCfg;            ///< settings for VSB PGA

	struct SCfgPreSaw      m_vsbPreSawCfg;         ///< settings for pre SAW sense

	s32            m_Quality83percent;     ///< MER level (*0.1 dB) for 83% quality indication

	s32            m_Quality93percent;     ///< MER level (*0.1 dB) for 93% quality indication

	s32    m_sysClockFreq;      /**< system clock frequency in kHz */



	enum EDrxkState    m_DrxkState;      /**< State of Drxk (init,stopped,started) */

	enum OperationMode m_OperationMode;  /**< digital standards */

	struct SCfgAgc     m_vsbRfAgcCfg;    /**< settings for VSB RF-AGC */

	struct SCfgAgc     m_vsbIfAgcCfg;    /**< settings for VSB IF-AGC */

	u16                m_vsbPgaCfg;      /**< settings for VSB PGA */

	struct SCfgPreSaw  m_vsbPreSawCfg;   /**< settings for pre SAW sense */

	s32    m_Quality83percent;  /**< MER level (*0.1 dB) for 83% quality indication */

	s32    m_Quality93percent;  /**< MER level (*0.1 dB) for 93% quality indication */

	bool   m_smartAntInverted;

	bool   m_bDebugEnableBridge;

	bool            m_bPDownOpenBridge;     ///< only open DRXK bridge before power-down once it has been accessed

	bool            m_bPowerDown;           ///< Power down when not used

	bool   m_bPDownOpenBridge;  /**< only open DRXK bridge before power-down once it has been accessed */

	bool   m_bPowerDown;        /**< Power down when not used */



	u32           m_IqmFsRateOfs;         ///< frequency shift as written to DRXK register (28bit fixpoint)

	u32    m_IqmFsRateOfs;      /**< frequency shift as written to DRXK register (28bit fixpoint) */



	bool   m_enableMPEGOutput;  /**< If TRUE, enable MPEG output */

	bool   m_insertRSByte;      /**< If TRUE, insert RS byte */
@@ -264,22 +261,22 @@ struct drxk_state { 
	u8     m_TSDataStrength;

	u8     m_TSClockkStrength;



	enum DRXMPEGStrWidth_t  m_widthSTR;          /**< MPEG start width**/

	enum DRXMPEGStrWidth_t  m_widthSTR;    /**< MPEG start width */

	u32    m_mpegTsStaticBitrate;          /**< Maximum bitrate in b/s in case

						    static clockrate is selected */



	//LARGE_INTEGER   m_StartTime;            ///< Contains the time of the last demod start

	s32            m_MpegLockTimeOut;      ///< WaitForLockStatus Timeout (counts from start time)

	s32            m_DemodLockTimeOut;     ///< WaitForLockStatus Timeout (counts from start time)

	/* LARGE_INTEGER   m_StartTime; */     /**< Contains the time of the last demod start */

	s32    m_MpegLockTimeOut;      /**< WaitForLockStatus Timeout (counts from start time) */

	s32    m_DemodLockTimeOut;     /**< WaitForLockStatus Timeout (counts from start time) */



	bool   m_disableTEIhandling;



	bool   m_RfAgcPol;

	bool   m_IfAgcPol;



	struct SCfgAgc         m_atvRfAgcCfg;          ///< settings for ATV RF-AGC

	struct SCfgAgc         m_atvIfAgcCfg;          ///< settings for ATV IF-AGC

	struct SCfgPreSaw      m_atvPreSawCfg;         ///< settings for ATV pre SAW sense

	struct SCfgAgc    m_atvRfAgcCfg;  /**< settings for ATV RF-AGC */

	struct SCfgAgc    m_atvIfAgcCfg;  /**< settings for ATV IF-AGC */

	struct SCfgPreSaw m_atvPreSawCfg; /**< settings for ATV pre SAW sense */

	bool              m_phaseCorrectionBypass;

	s16               m_atvTopVidPeak;

	u16               m_atvTopNoiseTh;
@@ -287,13 +284,13 @@ struct drxk_state { 
	bool              m_enableCVBSOutput;

	bool              m_enableSIFOutput;

	bool              m_bMirrorFreqSpect;

	enum EDrxkConstellation  m_Constellation;    ///< Constellation type of the channel

	u32           m_CurrSymbolRate;       ///< Current QAM symbol rate

	struct SCfgAgc         m_qamRfAgcCfg;          ///< settings for QAM RF-AGC

	struct SCfgAgc         m_qamIfAgcCfg;          ///< settings for QAM IF-AGC

	u16          m_qamPgaCfg;            ///< settings for QAM PGA

	struct SCfgPreSaw      m_qamPreSawCfg;         ///< settings for QAM pre SAW sense

	enum EDrxkInterleaveMode m_qamInterleaveMode; ///< QAM Interleave mode

	enum EDrxkConstellation  m_Constellation; /**< Constellation type of the channel */

	u32               m_CurrSymbolRate;       /**< Current QAM symbol rate */

	struct SCfgAgc    m_qamRfAgcCfg;          /**< settings for QAM RF-AGC */

	struct SCfgAgc    m_qamIfAgcCfg;          /**< settings for QAM IF-AGC */

	u16               m_qamPgaCfg;            /**< settings for QAM PGA */

	struct SCfgPreSaw m_qamPreSawCfg;         /**< settings for QAM pre SAW sense */

	enum EDrxkInterleaveMode m_qamInterleaveMode; /**< QAM Interleave mode */

	u16               m_fecRsPlen;

	u16               m_fecRsPrescale;
@@ -302,9 +299,9 @@ struct drxk_state { 
	u16               m_GPIO;

	u16               m_GPIOCfg;



	struct SCfgAgc         m_dvbtRfAgcCfg;          ///< settings for QAM RF-AGC

	struct SCfgAgc         m_dvbtIfAgcCfg;          ///< settings for QAM IF-AGC

	struct SCfgPreSaw      m_dvbtPreSawCfg;         ///< settings for QAM pre SAW sense

	struct SCfgAgc    m_dvbtRfAgcCfg;     /**< settings for QAM RF-AGC */

	struct SCfgAgc    m_dvbtIfAgcCfg;     /**< settings for QAM IF-AGC */

	struct SCfgPreSaw m_dvbtPreSawCfg;    /**< settings for QAM pre SAW sense */



	u16               m_agcFastClipCtrlDelay;

	bool              m_adcCompPassed;
@@ -328,7 +325,7 @@ struct drxk_state { 
	u16               m_AntennaDVBT;

	u16               m_AntennaSwitchDVBTDVBC;



	DRXPowerMode_t m_currentPowerMode;

	enum DRXPowerMode m_currentPowerMode;

};



#define NEVER_LOCK 0