Commit ec8bf725 authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
Browse files

staging: comedi: ni_stc.h: tidy up AO_Mode_2_Register and bits 



Rename the CamelCase and convert the enum into defines. Use the BIT()
macro to define the bits.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4e5ce0a8

drivers/staging/comedi/drivers/ni_mio_common.c

+14 −14
Original line number Diff line number Diff line
@@ -345,7 +345,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = { 
	[NISTC_G0_INPUT_SEL_REG]	= { 0x148, 2 },

	[NISTC_G1_INPUT_SEL_REG]	= { 0x14a, 2 },

	[NISTC_AO_MODE1_REG]		= { 0x14c, 2 },

	[AO_Mode_2_Register]		= { 0x14e, 2 },

	[NISTC_AO_MODE2_REG]		= { 0x14e, 2 },

	[AO_UI_Load_A_Register]		= { 0x150, 4 },

	[AO_UI_Load_B_Register]		= { 0x154, 4 },

	[AO_BC_Load_A_Register]		= { 0x158, 4 },
@@ -2991,15 +2991,15 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
	ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);



	ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);

	devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;

	ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);

	devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC;

	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);

	if (cmd->stop_src == TRIG_NONE)

		ni_stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);

	else

		ni_stc_writel(dev, 0, AO_BC_Load_A_Register);

	ni_stc_writew(dev, NISTC_AO_CMD1_BC_LOAD, NISTC_AO_CMD1_REG);

	devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;

	ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);

	devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC;

	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);

	switch (cmd->stop_src) {

	case TRIG_COUNT:

		if (devpriv->is_m_series) {
@@ -3055,9 +3055,9 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
	}

	ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG);

	ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);

	devpriv->ao_mode2 &=

	    ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);

	ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);

	devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) |

			       NISTC_AO_MODE2_UI_INIT_LOAD_SRC);

	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);



	if (cmd->scan_end_arg > 1) {

		devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN;
@@ -3087,14 +3087,14 @@ static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s) 
	devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;

	ni_stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);



	devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;

	devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK;

#ifdef PCIDMA

	devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;

	devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F;

#else

	devpriv->ao_mode2 |= AO_FIFO_Mode_HF;

	devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF;

#endif

	devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;

	ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);

	devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA;

	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);



	bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |

	    AO_TMRDACWR_Pulse_Width;
@@ -3231,7 +3231,7 @@ static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s) 
	devpriv->ao_mode1 = 0;

	ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG);

	devpriv->ao_mode2 = 0;

	ni_stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);

	ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG);

	if (devpriv->is_m_series)

		devpriv->ao_mode3 = AO_Last_Gate_Disable;

	else

drivers/staging/comedi/drivers/ni_stc.h

+20 −21
Original line number Diff line number Diff line
@@ -232,6 +232,26 @@ 
#define NISTC_AO_MODE1_CONTINUOUS	BIT(1)

#define NISTC_AO_MODE1_TRIGGER_ONCE	BIT(0)



#define NISTC_AO_MODE2_REG		39

#define NISTC_AO_MODE2_FIFO_MODE(x)	(((x) & 0x3) << 14)

#define NISTC_AO_MODE2_FIFO_MODE_MASK	NISTC_AO_MODE2_FIFO_MODE(3)

#define NISTC_AO_MODE2_FIFO_MODE_E	NISTC_AO_MODE2_FIFO_MODE(0)

#define NISTC_AO_MODE2_FIFO_MODE_HF	NISTC_AO_MODE2_FIFO_MODE(1)

#define NISTC_AO_MODE2_FIFO_MODE_F	NISTC_AO_MODE2_FIFO_MODE(2)

#define NISTC_AO_MODE2_FIFO_MODE_HF_F	NISTC_AO_MODE2_FIFO_MODE(3)

#define NISTC_AO_MODE2_FIFO_REXMIT_ENA	BIT(13)

#define NISTC_AO_MODE2_START1_DISABLE	BIT(12)

#define NISTC_AO_MODE2_UC_INIT_LOAD_SRC	BIT(11)

#define NISTC_AO_MODE2_UC_WR_SWITCH	BIT(10)

#define NISTC_AO_MODE2_UI2_INIT_LOAD_SRC BIT(9)

#define NISTC_AO_MODE2_UI2_RELOAD_MODE	BIT(8)

#define NISTC_AO_MODE2_UI_INIT_LOAD_SRC	BIT(7)

#define NISTC_AO_MODE2_UI_RELOAD_MODE(x) (((x) & 0x7) << 4)

#define NISTC_AO_MODE2_UI_WR_SWITCH	BIT(3)

#define NISTC_AO_MODE2_BC_INIT_LOAD_SRC	BIT(2)

#define NISTC_AO_MODE2_BC_RELOAD_MODE	BIT(1)

#define NISTC_AO_MODE2_BC_WR_SWITCH	BIT(0)



#define AI_Status_1_Register		2

#define Interrupt_A_St				0x8000

#define AI_FIFO_Full_St				0x4000
@@ -286,27 +306,6 @@ enum Joint_Status_2_Bits { 
	AO_TMRDACWRs_In_Progress_St = 0x20,

};



#define AO_Mode_2_Register		39

#define AO_FIFO_Mode_Mask (0x3 << 14)

enum AO_FIFO_Mode_Bits {

	AO_FIFO_Mode_HF_to_F = (3 << 14),

	AO_FIFO_Mode_F = (2 << 14),

	AO_FIFO_Mode_HF = (1 << 14),

	AO_FIFO_Mode_E = (0 << 14),

};

#define AO_FIFO_Retransmit_Enable		_bit13

#define AO_START1_Disable			_bit12

#define AO_UC_Initial_Load_Source		_bit11

#define AO_UC_Write_Switch			_bit10

#define AO_UI2_Initial_Load_Source		_bit9

#define AO_UI2_Reload_Mode			_bit8

#define AO_UI_Initial_Load_Source		_bit7

#define AO_UI_Reload_Mode(x)			(((x) & 0x7) << 4)

#define AO_UI_Write_Switch			_bit3

#define AO_BC_Initial_Load_Source		_bit2

#define AO_BC_Reload_Mode			_bit1

#define AO_BC_Write_Switch			_bit0



#define AO_UI_Load_A_Register		40

#define AO_UI_Load_A_Register_High	40

#define AO_UI_Load_A_Register_Low	41