Commit ece6fb06 authored by Chengming Gui's avatar Chengming Gui Committed by Alex Deucher
Browse files

drm/amd/amdgpu: add mmhub support for beige_goby 



Same as dimgrey_cavefish

Signed-off-by: default avatarChengming Gui <Jack.Gui@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fd5b4b44

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

+6 −0
Original line number Diff line number Diff line
@@ -544,6 +544,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad 
	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

		break;
@@ -578,6 +579,7 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad 
	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

		if (def != data)

			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);

		if (def1 != data1)
@@ -601,6 +603,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade 
	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		break;

	default:
@@ -618,6 +621,7 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade 
		case CHIP_SIENNA_CICHLID:

		case CHIP_NAVY_FLOUNDER:

		case CHIP_DIMGREY_CAVEFISH:

		case CHIP_BEIGE_GOBY:

			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);

			break;

		default:
@@ -640,6 +644,7 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 
	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

		mmhub_v2_0_update_medium_grain_clock_gating(adev,

				state == AMD_CG_STATE_GATE);

		mmhub_v2_0_update_medium_grain_light_sleep(adev,
@@ -663,6 +668,7 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 
	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

		data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

		break;