Commit eddc917d authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: align SDHCI reg-names with DT schema 



DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
just like TXT bindings were expecting before the conversion.

Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220712144245.17417-4-krzysztof.kozlowski@linaro.org
parent f2819650

arch/arm64/boot/dts/qcom/ipq8074.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -383,7 +383,7 @@ spmi_bus: spmi@200f000 { 
		sdhc_1: mmc@7824900 {

			compatible = "qcom,sdhci-msm-v4";

			reg = <0x7824900 0x500>, <0x7824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/msm8916.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -1483,7 +1483,7 @@ lpass_codec: audio-codec@771c000 { 
		sdhc_1: mmc@7824000 {

			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";

			reg = <0x07824900 0x11c>, <0x07824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@@ -1501,7 +1501,7 @@ sdhc_1: mmc@7824000 { 
		sdhc_2: mmc@7864000 {

			compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4";

			reg = <0x07864900 0x11c>, <0x07864000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/msm8953.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -799,7 +799,7 @@ sdhc_1: mmc@7824900 { 
			compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";



			reg = <0x7824900 0x500>, <0x7824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@@ -859,7 +859,7 @@ sdhc_2: mmc@7864900 { 
			compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";



			reg = <0x7864900 0x500>, <0x7864000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/msm8994.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -459,7 +459,7 @@ usb@f9200000 { 
		sdhc1: mmc@f9824900 {

			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,

				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@@ -482,7 +482,7 @@ sdhc1: mmc@f9824900 { 
		sdhc2: mmc@f98a4900 {

			compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";

			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;

arch/arm64/boot/dts/qcom/msm8996.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -3023,7 +3023,7 @@ hsusb_phy2: phy@7412000 { 
		sdhc1: mmc@7464900 {

			compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";

			reg = <0x07464900 0x11c>, <0x07464000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,

					<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
@@ -3047,7 +3047,7 @@ sdhc1: mmc@7464900 { 
		sdhc2: mmc@74a4900 {

			compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";

			reg = <0x074a4900 0x314>, <0x074a4000 0x800>;

			reg-names = "hc_mem", "core_mem";

			reg-names = "hc", "core";



			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,

				      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;