Commit eeb036ab authored by Luca Ceresoli's avatar Luca Ceresoli Committed by Hans Verkuil
Browse files

staging: media: tegra-video: add H/V flip controls 



Tegra20 can do horizontal and vertical image flip, but Tegra210 cannot
(either the hardware, or this driver).

In preparation to adding Tegra20 support, add a flag in struct tegra_vi_soc
so the generic vi.c code knows whether the flip controls should be added or
not.

Also provide a generic implementation that simply sets two flags in the
channel struct. The Tegra20 implementation will enable flipping at stream
start based on those flags.

Signed-off-by: default avatarLuca Ceresoli <luca.ceresoli@bootlin.com>
Reviewed-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
parent b4e25722

drivers/staging/media/tegra-video/vi.c

+13 −1
Original line number Diff line number Diff line
@@ -30,7 +30,7 @@ 
#include "vi.h"

#include "video.h"



#define MAX_CID_CONTROLS		1

#define MAX_CID_CONTROLS		3



/**

 * struct tegra_vi_graph_entity - Entity in the video graph
@@ -912,6 +912,12 @@ static int vi_s_ctrl(struct v4l2_ctrl *ctrl) 
	case V4L2_CID_TEGRA_SYNCPT_TIMEOUT_RETRY:

		chan->syncpt_timeout_retry = ctrl->val;

		break;

	case V4L2_CID_HFLIP:

		chan->hflip = ctrl->val;

		break;

	case V4L2_CID_VFLIP:

		chan->vflip = ctrl->val;

		break;

	default:

		return -EINVAL;

	}
@@ -983,6 +989,12 @@ static int tegra_channel_setup_ctrl_handler(struct tegra_vi_channel *chan) 
		v4l2_ctrl_handler_free(&chan->ctrl_handler);

		return ret;

	}



	if (chan->vi->soc->has_h_v_flip) {

		v4l2_ctrl_new_std(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);

		v4l2_ctrl_new_std(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);

	}



#endif



	/* setup the controls */

drivers/staging/media/tegra-video/vi.h

+8 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ struct tegra_vi_ops { 
 * @hw_revision: VI hw_revision

 * @vi_max_channels: supported max streaming channels

 * @vi_max_clk_hz: VI clock max frequency

 * @has_h_v_flip: the chip can do H and V flip, and the driver implements it

 */

struct tegra_vi_soc {

	const struct tegra_video_format *video_formats;
@@ -83,6 +84,7 @@ struct tegra_vi_soc { 
	u32 hw_revision;

	unsigned int vi_max_channels;

	unsigned int vi_max_clk_hz;

	bool has_h_v_flip:1;

};



/**
@@ -172,6 +174,9 @@ struct tegra_vi { 
 * @tpg_fmts_bitmap: a bitmap for supported TPG formats

 * @pg_mode: test pattern generator mode (disabled/direct/patch)

 * @notifier: V4L2 asynchronous subdevs notifier

 *

 * @hflip: Horizontal flip is enabled

 * @vflip: Vertical flip is enabled

 */

struct tegra_vi_channel {

	struct list_head list;
@@ -222,6 +227,9 @@ struct tegra_vi_channel { 
	enum tegra_vi_pg_mode pg_mode;



	struct v4l2_async_notifier notifier;



	bool hflip:1;

	bool vflip:1;

};



/**