Loading Documentation/ABI/testing/sysfs-driver-bd9571mwv-regulator +1 −1 Original line number Diff line number Diff line Loading @@ -26,6 +26,6 @@ Description: Read/write the current state of DDR Backup Mode, which controls DDR Backup Mode must be explicitly enabled by the user, to invoke step 1. See also Documentation/devicetree/bindings/mfd/bd9571mwv.txt. See also Documentation/devicetree/bindings/mfd/rohm,bd9571mwv.yaml. Users: User space applications for embedded boards equipped with a BD9571MWV PMIC. Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +1 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ description: | The case where SH and SP are both 1 is likely not very interesting. maintainers: - Luca Ceresoli <luca@lucaceresoli.net> - Luca Ceresoli <luca.ceresoli@bootlin.com> properties: compatible: Loading Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt +1 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ has been processed. See [2] for more information on the brcm,l2-intc node. firmware. On some SoCs, this firmware supports DFS and DVFS in addition to Adaptive Voltage Scaling. [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml Node brcm,avs-cpu-data-mem Loading Documentation/devicetree/bindings/display/arm,malidp.yaml +1 −6 Original line number Diff line number Diff line Loading @@ -71,11 +71,6 @@ properties: - description: number of output lines for the green channel (G) - description: number of output lines for the blue channel (B) arm,malidp-arqos-high-level: $ref: /schemas/types.yaml#/definitions/uint32 description: integer describing the ARQoS levels of DP500's QoS signaling arm,malidp-arqos-value: $ref: /schemas/types.yaml#/definitions/uint32 description: Loading Loading @@ -113,7 +108,7 @@ examples: clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; arm,malidp-arqos-high-level = <0xd000d000>; arm,malidp-arqos-value = <0xd000d000>; port { dp0_output: endpoint { Loading Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +1 −1 Original line number Diff line number Diff line Loading @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU dt properties for SC7180 target maintainers: - Krishna Manikandan <mkrishn@codeaurora.org> - Krishna Manikandan <quic_mkrishn@quicinc.com> description: | Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates Loading Loading
Documentation/ABI/testing/sysfs-driver-bd9571mwv-regulator +1 −1 Original line number Diff line number Diff line Loading @@ -26,6 +26,6 @@ Description: Read/write the current state of DDR Backup Mode, which controls DDR Backup Mode must be explicitly enabled by the user, to invoke step 1. See also Documentation/devicetree/bindings/mfd/bd9571mwv.txt. See also Documentation/devicetree/bindings/mfd/rohm,bd9571mwv.yaml. Users: User space applications for embedded boards equipped with a BD9571MWV PMIC.
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml +1 −1 Original line number Diff line number Diff line Loading @@ -45,7 +45,7 @@ description: | The case where SH and SP are both 1 is likely not very interesting. maintainers: - Luca Ceresoli <luca@lucaceresoli.net> - Luca Ceresoli <luca.ceresoli@bootlin.com> properties: compatible: Loading
Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt +1 −1 Original line number Diff line number Diff line Loading @@ -16,7 +16,7 @@ has been processed. See [2] for more information on the brcm,l2-intc node. firmware. On some SoCs, this firmware supports DFS and DVFS in addition to Adaptive Voltage Scaling. [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt [2] Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml Node brcm,avs-cpu-data-mem Loading
Documentation/devicetree/bindings/display/arm,malidp.yaml +1 −6 Original line number Diff line number Diff line Loading @@ -71,11 +71,6 @@ properties: - description: number of output lines for the green channel (G) - description: number of output lines for the blue channel (B) arm,malidp-arqos-high-level: $ref: /schemas/types.yaml#/definitions/uint32 description: integer describing the ARQoS levels of DP500's QoS signaling arm,malidp-arqos-value: $ref: /schemas/types.yaml#/definitions/uint32 description: Loading Loading @@ -113,7 +108,7 @@ examples: clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; arm,malidp-arqos-high-level = <0xd000d000>; arm,malidp-arqos-value = <0xd000d000>; port { dp0_output: endpoint { Loading
Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml +1 −1 Original line number Diff line number Diff line Loading @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Display DPU dt properties for SC7180 target maintainers: - Krishna Manikandan <mkrishn@codeaurora.org> - Krishna Manikandan <quic_mkrishn@quicinc.com> description: | Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates Loading