Commit ef4b623b authored by Marc Kleine-Budde's avatar Marc Kleine-Budde
Browse files

can: flexcan: quirks: get rid of long lines 



This patch reformats the quirks to get rid of long lines.

Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
Link: https://lore.kernel.org/r/20200922144429.2613631-6-mkl@pengutronix.de
parent fe63a066

drivers/net/can/flexcan.c

+17 −8
Original line number Diff line number Diff line
@@ -184,14 +184,23 @@ 
 *

 * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.

 */

#define FLEXCAN_QUIRK_BROKEN_WERR_STATE	BIT(1) /* [TR]WRN_INT not connected */

#define FLEXCAN_QUIRK_DISABLE_RXFG	BIT(2) /* Disable RX FIFO Global mask */

#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS	BIT(3) /* Enable EACEN and RRS bit in ctrl2 */

#define FLEXCAN_QUIRK_DISABLE_MECR	BIT(4) /* Disable Memory error detection */

#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP	BIT(5) /* Use timestamp based offloading */

#define FLEXCAN_QUIRK_BROKEN_PERR_STATE	BIT(6) /* No interrupt for error passive */

#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN	BIT(7) /* default to BE register access */

#define FLEXCAN_QUIRK_SETUP_STOP_MODE		BIT(8) /* Setup stop mode to support wakeup */



/* [TR]WRN_INT not connected */

#define FLEXCAN_QUIRK_BROKEN_WERR_STATE BIT(1)

 /* Disable RX FIFO Global mask */

#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2)

/* Enable EACEN and RRS bit in ctrl2 */

#define FLEXCAN_QUIRK_ENABLE_EACEN_RRS  BIT(3)

/* Disable Memory error detection */

#define FLEXCAN_QUIRK_DISABLE_MECR BIT(4)

/* Use timestamp based offloading */

#define FLEXCAN_QUIRK_USE_OFF_TIMESTAMP BIT(5)

/* No interrupt for error passive */

#define FLEXCAN_QUIRK_BROKEN_PERR_STATE BIT(6)

/* default to BE register access */

#define FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN BIT(7)

/* Setup stop mode to support wakeup */

#define FLEXCAN_QUIRK_SETUP_STOP_MODE BIT(8)



/* Structure of the message buffer */

struct flexcan_mb {